近年來，消費者對行動及穿戴裝置的需求逐漸成長，電子產品朝向更輕、薄、短、小的設計趨勢也愈加明顯。影像感測器模組在行動及穿戴裝置中是一個關鍵零組件，影像感測器模組的尺寸大小也會直接影響電子產品的體積。因此，如何設計一個輕、薄、短、小的影像感測器模組變成一個重要課題，愈來愈多的研發資源也投入到相關領域。其中，縮小感光像素的尺寸是一個有效的方法來縮小影像感測器模組的體積。然而，此方法所要付出的代價是較差的動能範圍、較少的光電子儲存能力及較低的靈敏度。在本論文中，我們提出三種新技術來解決以上問題。
首先，一個利用二次曝光(長、短曝光)、單次讀取技術的寬動態範圍互補式金氧半導體影像感測器被提出。此影像感測器可達成行平行高低照度像素的偵測。並藉由此功能，可選擇性的讀取長曝光訊號(低照度像素)或短曝光訊號(高照度像素)並加以數位化。此「高低照度像素偵測」的功能己被整合在所提出的行平行類比數位轉換器中，因此每一個像素在讀取時，首先會執行高低照度像素的偵測，並根據偵測結果來讀取長曝光訊號或短曝光訊號，最終再合成一幅寬動態範圍的影像。相較於傳統的二次曝光或多次曝光技術，此方法可減少系統所需的記憶體容量及類比數位轉換器的執行次數，因此耗電可大幅降低。另外，此影像感測器動態範圍的大小可藉由調整長、短曝光時間的比例來加以控制。
另外，所提出的行類比數位轉換器還有另外一種操作模式，光電子儲存能力延展模式。此操作模式可解決傳統的四電晶體主動式像素感測器因像素尺寸微縮所造成光電子儲存能力降低的問題。傳統的四電晶體主動式像素感測器只將光電子儲存在光電二極體中，而在所提出的方法中，除了將光電子儲存在光電二極體中，一旦光電二極體所儲存的光電子達到了上限，多餘的光電子會溢位並儲存在浮動擴散層中，因此也增加了四電晶體主動式像素感測器的光電子儲存能力。所
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提出的行平行類比數位轉換器具有判斷是否有溢位的光電子儲存在浮動擴散層中的功能，並可累加儲存在光電二極體和浮動擴散層中的光電子。可減少行類比數位轉換器的執行次數並降低耗電。
最後，本論文提出一個內建自我測試功能的三維整合影像感測器層來縮小晶片面積。較小的晶片面積可有效縮小影像感測器模組的體積。所提出的三維整合影像感測器層是由許多的子像素陣列所組成，每個子像素陣列各自獨立且可平行運作。當子像素陣列的數目增加，影像感測器的解析度也變高，但影像感測器的畫面更新率卻可維持不變，這是此架構的最大優點。除此之外，所提出的內建自我測試電路可以在晶片堆疊前，偵測出不合格的晶片，以提升晶片堆疊後的良率。所提出的內建自我測試電路並不會增加像素電路的複雜度，因此整體影像感測器對光強度的靈敏度並不會因此下降。所提出的三維整合影像感測器層非常適合使用在需小影像感測器模組的應用上。

The fast growing demand of thin and compact mobile and wearable devices has driven the efforts to reduce the size of camera module. CMOS image sensor (CIS) with small pixel dimension is an effective solution to implement a small size camera module. The design challenges of CMOS image sensor with small pixel dimension are low dynamic range, low full well capacity (FWC) and low sensitivity. In this thesis, three new techniques are proposed to address the problems.
Firstly, a dual-exposure single-capture wide dynamic range CMOS image sensor for mobile devices is proposed. The proposed sensor achieves column-wise highly/lowly-illuminated pixel detection, and only the “adequate” voltage signal (long- or short-exposure signal) is digitized. With an integrated highly/lowly-illuminated pixel detection function in the column-wise single slope ADC, each pixel is read out only once with highly- or lowly-illuminated pixel index for synthesis of a wide DR frame. This approach can dramatically reduce the power dissipation compared to existing multi-frame-readout solutions. The dynamic range expansion ratio is programmable, and depends on the time ratio of long-exposure to short-exposure period.
Secondly, a novel single-slope ADC design and operation is proposed to expand full well capacity of CMOS image sensor with small pixel dimension. With the proposed technique, charges stored in the photodiode and floating diffusion of 4T active pixel sensor are all read out and accumulated by the proposed SS ADC to improve the FWC. Only one A/D conversion is required for each pixel, which decreases chip power consumption compared to the general double A/D conversion operation.
Finally, because 3D IC is an emerging solution to reduce chip size, a 3D-integrated
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CMOS image sensor layer with built-in self-test function for 3-layer stacking CMOS imager is proposed. A modular CIS sub-array is proposed with new readout and control scheme. The proposed readout structure with in-pixel two-dimensional (2D) decoding function achieves high spatial resolution, without degrading the frame rate. A BIST circuit is also proposed to filter out unqualified CIS layer before chip stacking, improving the yield performance of the final 3D integrated imagers, without adding extra transistor in the pixel. The proposed 3D-integrated CIS layer is very suitable for small size camera module applications.

[1] A. El Gamal and H. Eltoukhy, "CMOS image sensors," IEEE Circuits Devices Mag., vol. 21, no. 3, pp. 6–20, May/Jun. 2005.
[2] E. R. Fossum, ”CMOS Active Pixel Image Sensors: Past, Present, and Future,” 2008 [online] Available: http://www.ericfossum.com
[3] A. Theuwissen, "CMOS image sensors: State-Of-the-art and future perspectives," in Proc. 33rd European Solid State Circuits Conf. (ESSCIRC 2007), Sep. 2007, pp. 21–27.
[4] Z. Ignjatovic and M. F. Bocko, "A 0.88nW/pixel, 99.6 dB Linear-Dynamic-Range Fully-Digital Image Sensor Employing a Pixel-Level Sigma-Delta ADC," in Symp. VLSI Circuits, 2006. pp. 23-24.
[5] D. X. D. Yang, A. E. Gamal, B. Fowler, and H. Tian, "A 640x512 CMOS image sensor with ultrawide dynamic range floating-point pixel-level ADC," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1821-1834, Dec. 1999.
[6] D. Stoppa, A. Simoni, L. Gonzo, M. Gottardi, and G. F. Dalla Betta, "Novel CMOS image sensor with a 132-dB dynamic range," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1846-1852, Dec. 2002.
[7] N. Akahane, R. Ryuzaki, S. Adachi, K. Mizobuchi, and S. Sugawa, "A 200dB Dynamic Range Iris-less CMOS Image Sensor with Lateral Overflow Integration Capacitor using Hybrid Voltage and Current Readout Operation," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2006, pp. 1161-1162.
[8] D. Stoppa, M. Vatteroni, D. Covi, A. Baschirotto, A. Sartori, and A. Simoni, "A 120-dB Dynamic Range CMOS Image Sensor With Programmable Power Responsivity," IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1555-1563, Jul. 2007.
[9] P. Jong-Ho, M. Mitsuhito, K. Shoji, S. Masaaki, W. Yasuo, and O. Yukihiro, "A 142dB Dynamic Range CMOS Image Sensor with Multiple Exposure Time Signals," in Proc. IEEE A-SSCC. Tech. Papers, Nov. 2005, pp. 85-88.
[10] M. Mase, S. Kawahito, M. Sasaki, and Y. Wakamori, "A 19.5b dynamic range CMOS image sensor with 12b column-parallel cyclic A/D converters," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 350-351.
[11] M. Mase, S. Kawahito, M. Sasaki, Y. Wakamori, and M. Furuta, "A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2787-2795, Dec. 2005.
[12] M. Sasaki, M. Mase, S. Kawahito, and Y. Tadokoro, "A wide dynamic range CMOS image sensor with multiple short-time exposures," in Proc. IEEE Sensors Conf., Oct. 2004, pp. 967-972.
[13] L. Xinqiao and A. El Gamal, "Synthesis of high dynamic range motion blur free image from multiple captures," IEEE Trans. Circuits and Systems I, vol. 50, no. 4, pp. 530-539, Apr. 2003.
[14] O. Yadid-Pecht and E. R. Fossum, "Wide intrascene dynamic range CMOS APS using dual sampling," IEEE Trans. Electron Devices, vol. 44, no. 10, pp. 1721-1723, Oct. 1997.
[15] Y. Oike, A. Toda, T. Taura, A. Kato, H. Sato, M. Kasai, and T. Narabu, "A 121.8dB Dynamic Range CMOS Image Sensor using Pixel-Variation-Free Midpoint Potential Drive and Overlapping Multiple Exposures," in Proc. Int. Image Sensor Workshop, Jun. 2007, pp. 30-33.
[16] K. Dongsoo, C. Youngcheol, C. Jihyun, and H. Gunhee, "A Dual-Capture Wide Dynamic Range CMOS Image Sensor Using Floating-Diffusion Capacitor," IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2590-2594, Oct. 2008.
[17] S. Sugawa, N. Akahane, S. Adachi, K. Mori, T. Ishiuchi, and K. Mizobuchi, "A 100 dB dynamic range CMOS image sensor using a lateral overflow integration capacitor," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 352-353.
[18] N. Akahane, S. Sugawa, S. Adachi, K. Mori, T. Ishiuchi, and K. Mizobuchi, "A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 851-858, Apr. 2006.
[19] O. Yadid-Pecht, "Wide-dynamic-range sensors," Opt. Eng., vol. 38, pp. 1650-1660, Oct. 1999.
[20] S. G. Chamberlain, J. P. Y. Lee, “A novel wide dynamic range silicon photodetector and linear imaging array,” IEEE Trans. Electron Devices, vol. ED-31, no. 2, pp. 175-182, Feb. 1984.
[21] S. Kavadias, B. Dierickx, D. Scheffer, A. Alaerts, D. Uwaerts, and J. Boagaerts, “A logarithmic response CMOS image sensor with on-chip calibration,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp.1146-1152, Aug. 2000.
[22] M. Vatteroni, P. Valdastri, A. Sartori, A. Menciassi, and P. Dario, "Linear-Logarithmic CMOS Pixel With Tunable Dynamic Range," IEEE Trans. Electron Devices, vol. 58, no. 4, pp. 1108-1115, April. 2011.
[23] G. Jian and S. Sonkusale, "A High Dynamic Range CMOS Image Sensor for Scientific Imaging Applications," IEEE Sensors Journal, vol. 9, no. 10, pp. 1209-1218, Oct. 2009.
[24] PhotonFocus---High Dynamic Range Products. [Online]. Available: http://www.photonfocus.ch/html/eng/applications/applicationReportsDetail.php?id=11&catId=0
[25] P. Seitz and F. Lustenberger, “Photo sensor with pinned photodiode and sub-linear response,” U.S. Patent 0 224 765, Sep. 9, 2010.
[26] J. Burns, L. McIlrath, C. Keast, C. Lewis, A. Loomis, K. Warner, and P. Wyatt, "Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip," in IEEE ISSCC Dig. Tech. Papers, 2001, pp. 268-269.
[27] C. L. Chen, D. R. Yost, J. M. Knecht, D. C. Chapman, D. C. Oakley, L. J. Mahoney, J. P. Donnelly, A. M. Soares, V. Suntharalingam, R. Berger, V. Bolkhovsky, W. Hu, B. D. Wheeler, C. L. Keast, and D. C. Shaver, "Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits," in Proc. IEEE Int. Conf. 3DIC, 2009, pp. 1-4.
[28] K. Kiyoyama, K. Lee, T. Fukushima, H. Naganuma, H. Kobayashi, T. Tanaka, and M. Koyanagi, "A block-parallel signal processing system for CMOS image sensor with three-dimensional structure," in Proc. IEEE Int. Conf. 3DIC, 2010, pp. 1-4.
[29] H. Yoshikawa, A. Kawasaki, Tomoaki, Iiduka, Y. Nishimura, K. Tanida, K. Akiyama, M. Sekiguchi, M. Matsuo, S. Fukuchi, and K. Takahashi, "Chip Scale Camera Module (CSCM) using Through-Silicon-Via (TSV)," in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 476-477.
[30] H. H. S. Lee and K. Chakrabarty, "Test Challenges for 3D Integrated Circuits," IEEE Design & Test Comput., vol. 26, no. 5, pp. 26-35, Sep.-Oct. 2009.
[31] C.-Y. Lo, Y.-T. Hsing, L.-M. Denq, and C.-W. Wu, "SOC Test Architecture and Method for 3-D ICs," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 10, pp. 1645-1649, Oct. 2010.
[32] D. L. Lewis and H. H. S. Lee, "A scanisland based design enabling prebond testability in die-stacked microprocessors," in Proc. ITC, 2007, pp. 1-8.
[33] L. Lizarraga, S. Mir, and G. Sicard, "Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors," in Proc. VTS, 2009, pp. 189-194.
[34] S.-F. Yeh, C.-C. Hsieh, C.-J. Cheng, and C.-K. Liu, "A Dual-Exposure Single-Capture Wide Dynamic Range CMOS Image Sensor With Columnwise Highly/Lowly Illuminated Pixel Detection," IEEE Trans. Electron Devices, vol. 59, pp. 1948-1955, 2012.
[35] S.-F. Yeh, C.-C. Hsieh, and K.-Y. Yeh, "A 3 megapixel 100 Fps 2.8 μm Pixel Pitch CMOS Image Sensor Layer with Built-in Self-test for 3D Integrated Imagers," IEEE J. Solid-State Circuits, vol. 48, pp. 839-849, 2013.
[36] P. Denyer, D. Renshaw, G. Wang, M. Lu, and S. Anderson, “On-chip CMOS sensors for VLSI imaging systems,” in Proc. VLSI-91, 1991, pp. 157–166.
[37] J. Ohta, Smart CMOS Image Sensors and Applications. Boca Raton, FL: CRC Press, 2008.
[38] B. Fowler, A. El Gamal, and H. Tian, "Analysis of temporal noise in CMOS photodiode active pixel sensor", IEEE J. Solid-State Circuits, vol. 36, pp.92 -101 2001
[39] E. R. Fossum and D. B. Hondongwa, "A Review of the Pinned Photodiode for CCD and CMOS Image Sensors," IEEE J. Electron Devices Society, vol. 2, pp. 33-43, 2014.
[40] Y. Endo, Y. Nitta, H. Kubo. T. Murao, K. Shimomura, M. Kimura. K. Watanabe and S. Komori. “4-mocron pixel CMOS image sensor with low image lag and high-temperature operability.” In Proc. SPIE, vol. 5017, pages 196-204, Santa Clara, CA, Jan. 2003.
[41] I. Inoue, N. Tanaka, H. Yamashita, T. Uamaguchi, H. Ishiwata and H. Ihara. “Low-leakage-current and low-operating-voltage buried photodiode for a CMOS imager.” IEEE Trans. Electron Devices, 50(1): 43-47, Jan. 2003.
[42] S. F. Yeh, C. C. Hsieh, C. F. Chiu, and H. H. Tsai, “An Image Lag Free CMOS Image Sensor with Constant-Residue Reset,” in Proc. of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2011.
[43] N. Yang and K. Matou, "A CMOS log image sensor with on-chip FPN compensation," in Proc. European Solid State Circuits Conf. (ESSCIRC), 2001, pp. 101-104.
[44] G. Storm, R. Henderson, J. E. D. Hurwitz, D. Renshaw, K. Findlater, and M. Purcell, “Extended dynamic range from a combined linear-logarithmic CMOS image sensor,” IEEE J. Solid-State Circuits, vol.41, no.9, pp. 2095-2106, Sep. 2006.
[45] M. Vatteroni, P. Valdastri, A. Sartori, A. Menciassi, and P. Dario, “linear–logarithmic CMOS pixel with tunable dynamic range,” IEEE Trans. Electron Devices, vol.58, no.4, pp. 1108-1115, Apr. 2011.
[46] A. Belouchrani and K. Abed-Meraim, “Wide-dynamic-range CMOS image sensors-comparative performance analysis,” IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2446–2461, Nov. 2009.
[47] D. Yang and A. El Gamal, “Comparative analysis of SNR for image sensors with enhanced dynamic range,” Proc. SPIE, vol. 3649, pp. 197–211, Jan. 1999.
[48] S. Kavusi and A. El Gamal, “Quantitative study of high dynamic range image sensor architectures,” in Proc. SPIE—Electronic Imaging, Jan. 2004, vol. 5301, pp. 264–275.
[49] M. Furuta, Y. Nishikawa, T. Inoue, and S. Kawahito, "A High-Speed, High-Sensitivity Digital CMOS Image Sensor with a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters," IEEE J. Solid-State Circuits, vol. 42, pp. 766-774, 2007.
[50] T. Watabe, K. Kitamura, T. Sawamoto, T. Kosugi, T. Akahori, T. Iida, et al., "A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADCs," in IEEE ISSCC Dig. Tech. Papers, 2012, pp. 388-390.
[51] K. Kitamura, T. Watabe, T. Sawamoto, T. Kosugi, T. Akahori, T. Iida, et al., "A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters," IEEE Trans. Electron Devices, vol. 59, pp. 3426-3433, 2012.
[52] P. Jong-Ho, S. Aoyama, T. Watanabe, T. Akahori, T. Kosugi, K. Isobe, et al., "A 0.1e- vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCs," in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 268-269.
[53] S. Matsuo, T. J. Bales, M. Shoda, S. Osawa, K. Kawamura, A. Andersson, et al., "8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SA-ADC," IEEE Trans. Electron Devices, vol. 56, pp. 2380-2389, 2009.
[54] A. I. Krymski, N. E. Bock, N. Tu, D. V. Blerkom, and E. R. Fossum, “A high-speed, 240-frames/s, 4.1-megapixel CMOS sensor,” IEEE Trans. Electron Devices, vol. 50, no. 1, pp. 130–135, Jan. 2003.
[55] S. Kawahito, J.-H. Park, K. Isobe, S. Suhaidi, T. Iida, and T. Mizota, “A CMOS image sensor integrating column-parallel cyclic ADCs with on-chip digital error-correction circuits,” in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 56–57.
[56] W. Yang, O.-B. Kwon, J.-I. Lee, G.-T. Hwang, and S.-J. Lee, “An integrated 800 × 600 CMOS imaging system,” in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 1999, pp. 304–305.
[57] Y. Nitta, Y. Muramatsu, K. Amano, T. Toyama, J. Yamamoto, K. Mishina, A. Suzuki, T. Taura, A. Kato, M. Kikuchi, Y. Yasui, H. Nomura, and N. Fukushima, “High-speed digital double sampling with analog CDS on column parallel ADC architecture for low-noise active pixel sensor,” in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 2024–2031.
[58] S. Yoshihara, Y. Nitta, M. Kikuchi, K. Koseki, Y. Ito, Y. Inada, S. Kuramochi, H. Wakabayashi, M. Okano, H. Kuriyama, J. Inutsuka, A. Tajima, T. Nakajima, Y. Kudoh, F. Koga, Y. Kasagi, S. Watanabe, and T. Nomoto, “A 1/1.8-inch 6.4 M-pixel 60 frame/s CMOS image sensor with seamless mode change,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2998–3006, Dec. 2006.
[59] S. Yoshihara, Y. Nitta, M. Kikuchi, K. Koseki, Y. Ito, Y. Inada, et al., "A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change," IEEE J. Solid-State Circuits, vol. 41, pp. 2998-3006, 2006.
[60] T. Sugiki, S. Ohsawa, H. Miura, M. Sasaki, N. Nakamura, I. Inoue, M. Hoshino, Y. Tomizawa, and T. Arakawa, “A 60mW10 b CMOS image sensor with column-to-column FPN reduction,” in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2000, pp. 108–109.
[61] Sony ---- News Releases [Online] Available: http://www.sony.net/SonyInfo/News/Press/200806/08-069E/index.html, June, 2008.
[62] S. G. Wuu, C .C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh and L. Tran, "A leading-edge 0.9um pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling," IEEE IEDM Tech. Dig., 2010, pp. 14.1.1-14.1.4.
[63] H. Rhodes, D. Tai, Y. Qian, D. Mao, V. Venezia Wei Zheng, Z. Xiong, C. Y. Liu, K. C. Ku, S. Manabe, A. Shah, S. Sasidhar, P. Cizdziei, Z. Lin, A. Ercan, M. Bikumandla, R. Yang, P. Matagne, C. Yang, H. Yang, T. J. Dai, J. Li, S. G. Wuu, D. N. Yaung, C. C. Wang, J. C. Liu, C. S. Tsai, Y. L. Tu, T. H. Hsu, "The mass production of BSI CMOS image sensors," Int. Image Sensor Workshop, 2009.
[64] I. Takayanagi etc. “A 600×600 Pixel, 500 fps CMOS Image Sensor with a 4.4μm Pinned Photodiode 5-Transistor Global Shutter Pixel”, Int. Image Sensor Workshop, Ogunquit Maine, USA, 2007.
[65] Yang Liu “The Design of a High Dynamic Range CMOS Image Sensor in 110nm Technology", Master thesis, Delft University of Technology, page 19-20, August, 2012.
[66] K. Yasutomi, S. Itoh, and S. Kawahito, "A Two-Stage Charge Transfer Active Pixel CMOS Image Sensor With Low-Noise Global Shuttering and a Dual-Shuttering Mode," IEEE Trans. Electron Devices, vol. 58, pp. 740-747, 2011.
[67] V. Suntharalingam, R. Berger, J. A. Burns, C. K. Chen, C. L. Keast, J. M. Knecht, R. D. Lambert, K. L. Newcomb, D. M. O'Mara, D. D. Rathman, D. C. Shaver, A. M. Soares, C. N. Stevenson, B. M. Tyrrell, K. Warner, B. D. Wheeler, D. R. W. Yost, and D. J. Young, "Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 356-357.
[68] V. Suntharalingam, R. Berger, S. Clark, J. Knecht, A. Messier, K. Newcomb, D. Rathman, R. Slattery, A. Soares, C. Stevenson, K. Warner, D. Young, A. Lin Ping, B. Mansoorian, and D. Shaver, "A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor," in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 38-39.
[69] H.-M. Chang, J.-L. Huang, D.-M. Kwai, K.-T. Cheng, and C.-W. Wu, "An error tolerance scheme for 3D CMOS imagers," in Proc. IEEE/ACM DAC, 2010, pp. 917-922.
[70] J. Aoki, Y. Takemoto, K. Kobayashi, N. Sakaguchi, M. Tsukimura, N. Takazawa, et al., "A rolling-shutter distortion-free 3D stacked image sensor with -160dB parasitic light sensitivity in-pixel storage node," in IEEE ISSCC Dig. Tech. Papers, 2013 IEEE International, 2013, pp. 482-483.
[71] S. Sukegawa, T. Umebayashi, T. Nakajima, H. Kawanobe, K. Koseki, I. Hirota, et al., "A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor," in IEEE ISSCC Dig. Tech. Papers, 2013, pp. 484-485.
[72] Sony ---- News Releases [Online] Available: http://www.imaging-resource.com/news/2012/01/23/sony-next-gen-sensors-improve-resolution-low-light-shooting
[73] P. Lichtsteiner, C. Posch and T. Delbruck., "A 128x128 120 dB 15us Latency Asynchronous Temporal Contrast Vision Sensor," IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 566-576, Feb. 2008.
[74] P. F. Ruedi, P. Heim, S. Gyger, F. Kaess, C. Arm, R.Caseiro, J. L. Nagel and S. Todeschini, "An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2009, pp. 46-47.
[75] M. Vatteroni, D. Covi and A. Sartori, "A linear-logarithmic CMOS pixel for high dynamic range behavior with fixed-pattern-noise correction and tunable responsivity," in Proc. IEEE Sensors Conf., Oct. 2008, pp. 930-933.
[76] OmniVision---High Dynamic Range Products. [Online]. Available: http://www.ovt.com/products/sensor.php?id=70
[77] Sonix---Optical Identification. [Online]. Available: http://www.sonix.com.tw/sonix/oidSolution.jsp.
[78] L. Yong, K. Kyoungmin, K. Kyungmin, Y. Han, K. Juha, J. Youngkyun, L. Seungjin, L. Hansoo, L. Sin-Hwan, H. Yunseok, K. Jinwoo, Y. Jaecheol, H. Seogheon, and L. Yun-Tae, "A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2010, pp. 396-397.
[79] T. Azuma, T. Imagawa, S. Ugawa, Y. Okada, H. Komobuchi, M. Ishii, S. Kasuga, and Y. Kato, "A 2.2/3-inch 4K2K CMOS image sensor based on dual resolution and exposure technique," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2010, pp. 408-409.
[80] H. Wakabayashi, K. Yamaguchi, M. Okano, S. Kuramochi, O. Kumagai, S. Sakane, M. Ito, M. Hatano, M. Kikuchi, Y. Yamagata, T. Shikanai, K. Koseki, K. Mabuchi, Y. Maruyama, K. Akiyama, E. Miyata, T. Honda, M. Ohashi, and T. Nomoto, "A 1/2.3-inch 10.3Mpixel 50frame/s Back-Illuminated CMOS image sensor," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2010, pp. 410-411.
[81] L. Sangjoo, L. Kyungho, P. Jongeun, H. Hyungjun, P. Younghwan, J. Taesub, J. Youngheup, K. Bumsuk, K. Yitae, S. Hamami, U. Hizi, M. Bahar, M. Changrok, A. JungChak, L. Duckhyung, H. Goto, and L. Yun-Tae, "A 1/2.33-inch 14.6M 1.4um-pixel backside-illuminated CMOS image sensor with floating diffusion boosting," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2011, pp. 416-417.
[82] T. Toyama, K. Mishina, H. Tsuchiya, T. Ichikawa, H. Iwaki, Y. Gendai, H. Murakami, K. Takamiya, H. Shiroshita, Y. Muramatsu, and T. Furusawa, "A 17.7Mpixel 120fps CMOS image sensor with 34.8Gb/s readout," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2011, pp. 420-421.
[83] M. Sakakibara, Y. Oike, T. Takatsuka, A. Kato, K. Honda, T. Taura, T. Machida, J. Okuno, A. Ando, T. Fukuro, T. Asatsuma, S. Endo, J. Yamamoto, Y. Nakano, T. Kaneshige, I. Yamamura, T. Ezaki, and T. Hirayama, "An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2012, pp. 380-381.
[84] Y. Oike and A. E. Gamal, "A 256×256 CMOS Image Sensor with ΔΣ-Based Single-Shot Compressed Sensing," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2012, pp. 386-387.
[85] N. Tanaka, J. Naruse, A. Mori, R. Okamoto, H. Yamashita, and M. Monoi, "A 1/2.5-inch 8Mpixel CMOS image sensor with a staggered shared-pixel architecture and an FD-boost operation," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2009, pp. 44-45.
[86] Y. Egawa, N. Tanaka, N. Kawai, H. Seki, A. Nakao, H. Honda, Y. Lida, and M. Monoi, "A White-RGB CFA-Patterned CMOS Image Sensor with Wide Dynamic Range," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2008, pp. 52-53.
[87] C. Kwang-Bo, L. Chiajen, S. Eikedal, A. Baum, J. Jutao, X. Chen, F. Xiaofeng, and R. Kauffman, "A 1/2.5 inch 8.1Mpixel CMOS Image Sensor for Digital Cameras," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2007, pp. 508-509.
[88] H. Takahashi, T. Noda, T. Matsuda, T. Watanabe, M. Shinohara, T. Endo, S. Takimoto, R. Mishima, S. Nishimura, K. Sakurai, H. Yuzurihara, and S. Inoue, "A 1/2.7 inch Low-Noise CMOS Image Sensor for Full HD Camcorders," in Proc. IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2007, pp. 510-511.
[89] M. Sasaki, M. Mase, S. Kawahito, and Y. Tadokoro, "A Wide-Dynamic-Range CMOS Image Sensor Based on Multiple Short Exposure-Time Readout With Multiple-Resolution Column-Parallel ADC," IEEE Sensors J., vol. 7, no. 1, pp. 151-158, Jan. 2007.
[90] D. Durini, F. Matheis, C. Nitta, W. Brockherde, and B. J. Hosticka, "Large full-well capacity stitched CMOS image sensor for high temperature applications," in Proc. IEEE ESSCIRC, 2010, pp. 130-133.
[91] M. Kasano, Y. Inaba, M. Mori, S. Kasuga, T. Murata, and T. Yamaguchi, "A 2.0-um pixel pitch MOS image sensor with 1.5 transistor/pixel and an amorphous Si color filter," IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 611-617, Apr. 2006.
[92] N. Akahane, S. Adachi, K. Mizobuchi, and S. Sugawa, "Optimum Design of Conversion Gain and Full Well Capacity in CMOS Image Sensor With Lateral Overflow Integration Capacitor," IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2429-2435, Nov. 2009.
[93] L. Woonghee, N. Akahane, S. Adachi, K. Mizobuchi, and S. Sugawa, "A high S/N ratio and high full well capacity CMOS image sensor with active pixel readout feedback operation," in Proc. IEEE ASSCC, 2007, pp. 260-263.
[94] M. Koyanagi, T. Fukushima, and T. Tanaka, "Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding," in IEEE Custom Integrated Circuits Conf. (CICC), Dig. Tech. Papers, 2010, pp. 1-4.
[95] K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, "3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proc. IEEE, vol. 89, no. 5, pp. 602-633, May 2001.
[96] M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T. Fukushima, T. Tanaka, and H. Kurino, "Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections," IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2799-2808, Nov. 2006.
[97] M.-F. Chang, W.-C. Wu, C.-S. Lin, P.-F. Chiu, M.-B. Chen, Y.-H. Chen, H.-C. Lai, Z.-H. Lin, S.-S. Sheu, T.-K. Ku, and H. Yamauchi, "A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms," in Symp. VLSI Circuits, 2011, pp. 74-75.
[98] H. H. Nho, M. Horowitz, and S. S. Wong, "A high-speed, low-power 3D-SRAM architecture," in IEEE Custom Integrated Circuits Conf. (CICC), Dig. Tech. Papers, 2008, pp. 201-204.
[99] K. Puttaswamy and G. H. Loh, "3D-Integrated SRAM Components for High-Performance Microprocessors," IEEE Trans. Computers, vol. 58, no. 10, pp. 1369-1381, Oct. 2009.
[100] T. Yuh-Fang, W. Feng, X. Yuan, N. Vijaykrishnan, and M. J. Irwin, "Design Space Exploration for 3-D Cache," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 4, pp. 444-455, Apr. 2008.
[101] M. Kawano, N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, and S. Matsui, "Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer," IEEE Trans. Electron Devices, vol. 55, no. 7, pp. 1614-1620, July 2008.
[102] U. Kang, H.-J. chung, S. Heo, D.-H. Park, H. Lee, J. H. Kim, S.-H. Ahn, S.-H. Cha, J. Ahn, D. Kwon, J.-W. Lee, H.-S. Joo, W.-S. Kim, D. H. Jang, N. S. Kim, J.-H. Choi, T.-G. Chung, J.-H. Yoo, J. S. Choi, C. Kim, and Y.-H. Jun, "8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology," IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 111-119, Jan. 2010.
[103] S. Q. Gu, P. Marchal, M. Facchini, F. Wang, M. Suh, D. Lisk, and M. Nowak, "Stackable memory of 3D chip integration for mobile applications," in IEEE IEDM Dig. Tech. Papers, 2008, pp. 1-4.
[104] K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai, and K. Takeuchi, "A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD," in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 238-239.
[105] C. Jungdal and S. Kwang Soo, "3D approaches for non-volatile memory," in Symp. VLSI Technology (VLSIT), 2011, pp. 178-179.
[106] G. Van der Plas, P. Limaye, I. Loi, A. Mercha, H. Oprins, C. Torregiani, S. Thijs, D. Linten, M. Stucchi, G. Katti, D. Velenis, V. Cherman, B. Vandevelde, V. Simons, I. De Wolf, R. Labie, D. Perry, S. Bronckers, N. Minas, M. Cupac, W. Ruythooren, J. Van Olmen, A. Phommahaxay, M. de Potter de ten Broeck, A. Opdebeeck, M. Rakowski, B. De Wachter, M. Dehan, M. Nelis, R. Agarwal, A. Pullini, F. Angiolini, L. Benini, W. Dehaene, Y. Travaly, E. Beyne, and P. Marchal, "Design Issues and Considerations for Low-Cost 3-D TSV IC Technology," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 293-307, Jan. 2011.
[107] S.-F. Yeh, J.-Y. Lin, C.-C. Hsieh, K.-Y. Yeh, and C.-C. J. Li, "A new CMOS image sensor readout structure for 3D integrated imagers," in IEEE Custom Integrated Circuits Conf. (CICC), Dig. Tech. Papers, 2011, pp. 1-4.
[108] H. Takahashi, M. Kinoshita, K. Morita, T. Shirai, T. Sato, T. Kimura, H. Yuzurihara, S. Inoue, and S. Matsumoto, "A 3.9-μm pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2417-2425, Dec. 2004.
[109] J. Nakamura, Ed., Image Sensors and Signal Processing For Digital Still Cameras. New York: Taylor & Francis, 2006, pp. 179–203.
[110] L. Woonghee, N. Akahane, S. Adachi, K. Mizobuchi, and S. Sugawa, "A 1.9 e- Random Noise CMOS Image Sensor With Active Feedback Operation in Each Pixel," IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2436-2445, Nov. 2009.
[111] Y. Chen, X. Yang, C. Youngcheol, A. Mierop, W. Xinyang, and A. Theuwissen, "A 0.7e-rms-Temporal-Readout-Noise CMOS Image Sensor for Low-Light-Level Imaging," in IEEE ISSCC Dig. Tech. Papers, 2012, pp. 384-385.
[112] C. Youngcheol, C. Jimin, L. Seunghyun, L. Dongmyung, K. Minho, Y. Kwisung, J. Wunki, L. Dong-Hun, H. Seogheon, and H. Gunhee, "A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel △ΣADC architecture," in IEEE ISSCC Dig. Tech. Papers, 2010, pp. 394-395.