本實驗中，我們提出一個可應用於未來CMOS導線的新技術，以自動對準的方式，將奈米碳管成長於連接孔底部的鎢磷化鈷(CoWP)金屬性銅擴散阻絕層上，鎢磷化鈷能有效降低銅電致遷移，且依ITRS roadmap預測，2006年將實際應用於半導體元件；同時，奈米碳管因具有超高電流承載力(Jmax > 109 A/cm2)、高傳熱性、高熱穩定性及高機械強度等優點，相當有潛力作為將來元件連線的材料。
本實驗著重於合成低阻值、高奈米碳管密度的連接孔，製程溫度為400 ℃，且以鎢磷化鈷作為催化劑。本實驗深具挑戰性，第一，需符合半導體後段製程要求，於400 ℃的低溫下合成奈米碳管，第二則是以鎢磷化鈷為奈米碳管催化劑。本實驗結果顯示可成功地將高密度(9.23x1010 cm-2)的奈米碳管成長在15 nm的鎢磷化鈷上，且已進一步將奈米碳管合成於100 nm的連接孔內，目前密度可達1.3x1011 cm-2，而由奈米碳管連接孔的電流¬-電壓圖，奈米碳管連接孔展現相當好的毆姆導体性質，目前每個100 nm的連接孔電阻為13.5 kΩ；目前的實驗結果顯示此低複雜度的製程實際應用的可能性，並且透過此方法，可降低製程複雜度及提升元件效能。

In this work, we propose a new self-aligned process that integrates CNT via and pre-existing cobalt tungsten phosphide (CoWP) metal barrier at the via bottom as a catalyst for future CMOS interconnect applications. The CoWP is an effective Cu diffusion barrier, which is anticipated to be used in real devices in 2006 according to ITRS roadmap. Moreover, CNT has extremely high current density capability (Jmax > 109 A/cm2), thermal conductivity, thermal stability, and mechanical strength, which make it a very promising material for future interconnect.
The focus of this work is to grow low-resistance and high-density CNTs into fine-feature and high aspect ratio via holes at 400 ℃ utilizing CoWP as the catalyst. The first challenge is to grow CNTs at 400 ℃, which is the requirement of IC back-end process. The second challenge is to synthesize CNTs using CoWP as a catalyst, which has never been done before. Experimental results showed that CNTs with a density of 9.23x1010 /cm2 were successfully grown on CoWP thin film after series of process optimization. We further grew CNTs with a density of about 1.3x1011 cm-2 in Cu dual damascene structure with a via size of only 100 nm. The I-V curve of these CNT vias show ohmic characteristics with an average via resistance of 13.5 kΩ/via. These results demonstrated the feasibility of this simplified self-aligned process for future CMOS interconnect by integrating CoWP barrier and CNT via to greatly reduce the process complexity and improve the device performance.

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