隨著無線通訊的進步，無線接收機在設計上的難度也更加困難。對於在基頻的放大器和濾波器而言，頻寬和能量消耗將是一個新的課題。一個可變增益放大器在接收機中，他所扮演的角色為減少類比至數位轉換器動態範圍的需求，且也需要低雜訊和高線性度上的要求。
一個具高動態範圍、低能量消耗、低雜訊和高線性度的可變增益放大器將是一個新的挑戰。
在基頻放大器通常有個嚴重的課題，即直流補偏移電壓。一個小的直流補偏移電壓經由高增益的基頻放大器，將直接破壞直流訊號或飽和下一及電路，致使整個無線接收機無法正常工作。一般的解決方式在使用大電容值來達到直流補偏移電壓消除的功能，但在晶片上大量使用被動元件將直接在成本上反應出缺點。一個以數位方式來達到直流補偏移電壓消除的功能的可變增益放大器將是一個可能的解決方式。
此論文實現一個互補式金屬半導體氧化物的數位控制可變增益放大器。此可變增益放大器採用衰減式放大器的特性來達到改變電壓增益的功用，也採用超級源級隨耦器的特性來當輸入級以致於可達到較高的線性度，並採用以數位電路為主的直流偏移電壓自我校正迴路來減少電路輸出的直流偏移電壓。
此晶片採用聯電0.18 µm互補式金屬半導體氧化物製程並且總共佔 。此可變增益放大器可以提供從-6 dB到58 dB的增益範圍，且以2 dB為一個間距。在1.8 V的電源供應器之前提下，此晶片共消耗6.12 MA的電流。總諧波失真在輸入訊號頻率在1 MHz和輸出擺幅在 下，在最小增益時為-48 dB。輸入三階點為4 dBV在最小增益時。輸入雜訊為12.3 在增一為最大時。在直流偏移電壓自我校正迴路正常遭操作下，輸入20 mV的直流偏移電壓，在最大增益時，輸出直流偏移電壓可小於100 mV。

This thesis implements a complementary metal oxide semiconductor (CMOS) VGA with digitally controlled gain. This VGA adopts the degeneration type amplifier to vary voltage gain and uses the super source follower input stage to enhance the linearity. And a digital based DC offset calibration loop is proposed to achieve the DC offset cancellation.

An experimental chip is fabricated in UMC 0.18 µm CMOS process and its total area . The VGA provide 64 dB gain range with 2 dB step and more than 10 MHz bandwidth. The current consumption from a single 1.8 V supply is less than 6.12 mA. The total harmonic distortion (THD) is small than -48 dB at the minimum gain setting when input signal operates at a 1 MHz and less than output swing. The input third intercept point (IIP3) is 4 dBV at minimum gain setting. The input referred noise is 12.3 at maximum gain setting. The output DC offset is less than the 100mV when 20 mV input DC offset is applied under after calibration operation.

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