可應用於無線感測網路與生醫設備的十位元低功耗連續近似類比數位轉換器利用電荷平均切換數位類比轉換器技術

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研究生：	劉昌淵 Liou, Chang-Yuan
論文名稱：	可應用於無線感測網路與生醫設備的十位元低功耗連續近似類比數位轉換器利用電荷平均切換數位類比轉換器技術 A 10-bit power-efficient SAR ADC with charge average switching DAC for wireless sensor network and biomedical device applications
指導教授：	謝志成 Hsieh, Chih-Cheng
口試委員:	李泰成張順志洪浩喬
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2013
畢業學年度：	101
語文別：	英文
論文頁數：	69
中文關鍵詞：	連續近似類比數位轉換器、電荷平均切換、數位類比轉換器、切換功耗、高能源效率
外文關鍵詞：	SAR ADC, Charge Average Switching, DAC, Switching energy, High energy efficiency
相關次數：	點閱：2 下載：0
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本論文提出一個十位元低電壓及高能源效率的連續近似(SAR)類比數位轉換器(ADC)，應用於無線網絡系統及生醫設備。
所提出的類比數位轉換器為了節省功率消耗操作在超低電壓，從0.4伏特至0.7伏特，所提出的類比數位轉換器在低電壓操作下利用多種技巧來提高能源效率，首先提出一個電荷平均切換方法(CAS)降低數位類比轉換器(DAC)的切換功耗，並減輕了開關緩衝器在高速轉換中的驅動需求，此方法沒有共模電壓變異和額外的參考電壓產生器，在低壓操作下增進了線性度以及能源效率，此外，一個自我控制的可變延遲時間控制器用來優化數位類比轉換器的穩定時間進而提高電路的操作頻率。
此架構使用標準90奈米1P9M互補式金氧半導體製程製作，晶片面積為110×380μm2，在0.4至0.7伏電源電壓及0.5至4百萬取樣頻率操作下，此晶片實現SNDR從54.3至56.3dB對應的ENOB為8.73至9.06在Nyquist輸入訊號頻率下，功率消耗為0.5至11微瓦，等效的figure of merit (FOM)為2.4至5.2fJ/conversion-step。

This thesis presents a 10-bit low-voltage and high power efficiency successive approximation register (SAR) analog-to- digital converter (ADC) for wireless sensor networks and biomedical devices applications.
The proposed ADC operates at ultra-low supply voltage from 0.4V to 0.7V to save power consumption. Several techniques are utilized to improve the power efficiency of the ADC in low voltage operation. The charge-average switching (CAS) technique is proposed to reduce digital-to-analog converter (DAC) switching energy and relax the driving requirement of switch buffer at high speed conversion phase. Without common-mode voltage variation and extra reference generator, improves the linearity and power efficiency at low voltage operation. A self-time variable delay controller optimizes the settling time of DAC improving the conversion speed.
The prototype was fabricated using 90nm 1P9M CMOS technology and core area is only 110×380μm2. At 0.4-to-0.7V supply and 0.5-to-4MS/s sampling rate, the ADC achieves SNDR from 54.3 to 56.3dB corresponding ENOB from 8.73 to 9.06 at Nyquist-rate input and consumes 0.5-to-11μW power consumption, resulting in a figure of merit (FOM) from 2.4 to 5.2fJ/conversion-step.

Abstract    II
Contents    V
List of Figures    VIII
List of Tables    XI
Chapter1  Introduction    1
1    Architecture Selection    2
2    Performance Metrics of SAR ADC    3
2.1    Resolution    4
2.2    Nyquist Criterion    4
2.3    Quantization Error    4
2.4    Differential Nonlinearity (DNL)    5
2.5    Integral Nonlinearity (INL)    5
2.6    Offset and Gain Error    5
2.7    Signal-to-Noise Ratio (SNR)    6
2.8    Effective Number of Bit (ENOB)    6
2.9    Figure of Merit (FOM)    6
3    Motivation    6
4    Target Specifications    7
5    Thesis Organization    8
Chapter2  Successive Approximation Register (SAR) ADC Overview    9
1    Conventional Single-Ended SAR ADC    9
2    Error Terms of Sample and Hold    10
2.1    On-Resistance of MOS Switch    11
2.2    Charge Injection    12
2.3    Clock Feedthrough    13
2.4    kT/C Noise    14
3    Error Terms of Capacitive DAC    14
3.1    DAC Parasitic Capacitance    15
3.2    DAC Capacitor Mismatch    16
4    Error Terms of Comparator    16
4.1    Comparator Input Offset    17
4.2    Comparator Kickback Noise    17
5    Digital SAR Control Logic    18
6    Summary    19
Chapter3  Circuit Design Considerations    20
1    Conventional Differential-type SAR ADC    20
2    CDAC Switching Energy    22
2.1    Conventional DAC Switching    22
2.2    Vcm-base DAC Switching    24
2.3    Monotonic DAC Switching    27
2.4    Switchback DAC Switching    29
2.5    Concepts of Proposed CAS DAC Technique    32
3    Sample and Hold Design Consideration    33
4    Comparator Design Consideration    34
5    Digital SAR Control Design Consideration    35
6    Summary    35
Chapter4  ADC implementation    36
1    ADC Architecture and DAC Design    36
2    Sample and Hold (S/H) Design    44
3    Dynamic Comparator Design    45
4    Digital SAR Control Logic Design    46
5    Pre-Layout and Post-Layout Simulation Results    48
6    Summary    50
Chapter5  Measurement Results    51
1    Measurement Environment Setup    51
2    Measurement Parameter Setup    52
3    Static Performance    53
4    Dynamic Performance    53
5    Performance Summary and Comparison    56
6    Summary    58
Chapter6  Conclusion and Future Work    60
1    Conclusion    60
2    Future Work    60
Bibliography    65

                                

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