整合性被動元件 (IPD) 被廣泛的運用於半導體晶片的先進封裝技術中，用於改善其電源完整性及阻抗匹配問題。對於應用於極高安全需求 (safety-critical) 產品中的晶片，如應用於汽車、航空、工業、國防系統等，保證其信號及電源完整性的需求日益增長，而在這些產品中整合性被動元件有助於提升晶片的品質與可靠性。然而若一個失效的整合性被動元件被整合至系統當中，將造成系統錯誤，進而導致高昂的報廢成本 (scrap cost)，因此在將整合性被動元件黏貼到其他的晶片上之前，篩選出失效的整合性被動元件變得至關重要。在本篇論文中，為了分辨出具有潛在可靠性問題的整合性被動元件，我們提出了一種基於機器學習 (machine learning) 的篩選方法。本論文所提出的半導體質量網 (Semiconductor Quality Net) 基於360,000個整合性被動元件的晶圓測試 (wafer probing test) 資料進行訓練，以預測具有較低擊穿電壓 (BV) 亦即具有低可靠性的整合性被動元件。當我們將過度誤殺率 (overkill rate) 限制於10%以下，本論文的方法可比現有工業上所使用的方法，即DPAT和GDBC，多篩選出6到15倍的失效的整合性被動元件。另外本論文也提出一個簡單的方法，讓工程師在實際應用時可以選擇一個最適當的方案來平衡整合性被動元件的品質、可靠性以及製造成本。

Integrated passive devices (IPDs) have been widely used in advanced packaging of semiconductor chips, to improve their power integrity and impedance matching. There is a growing demand in guaranteeing signal and power integrity for the chips used in safety-critical products, such as those used in automotive, aviation, industrial, and defense systems, where IPDs help improve the quality and reliability of the chips. Therefore, IPD testing and screening itself is essential. Note that the scrap cost caused by failed IPDs is much higher than the cost of manufacturing the IPDs, so screening bad IPDs before mounting is also crucial. In this work, we propose a machine learning (ML) based screening methodology to identifying the IPDs that have potential reliability issues. Based on the parametric data of 360,000 IPDs collected from the wafer probing test, the proposed Semiconductor Quality Net (SQnet) is trained to predict the IPDs which have low breakdown voltage, i.e., low reliability. Keeping the overkill rate below 10%, our method can screen out 6 to 15X more bad dies than the existing industrial methods, i.e., DPAT and GDBC. Also, provides an easy way to find a solution that balances the quality/reliability need and manufacturing cost.

[1] J.-F. Li and C.-W. Wu, “Is 3D Integration an Opportunity or Just a Hype?,” in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Taipei, pp. 541-543, Jan. 2010.
[2] C.-C. Chi, C.-W. Wu, M.-J. Wang, and H.-C. Lin, “3D-IC Interconnect Test, Diagnosis, and Repair,” in Proc. 31st IEEE VLSI Test Symp. (VTS), Berkeley, CA, pp. 1-6, Apr. 2013.
[3] C.-C. Chi, B.-Y. Lin, C.-W. Wu, M.-J. Wang, H.-C. Lin, and C.-N. Peng, “On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs,” IEEE Design & Test, vol. 31, no. 4, pp. 16-26, Aug. 2014.
[4] A. Yoshida, J. Taniguchi, K. Murata, M. Kada, Y. Yamamoto, Y. Takagi, T. Notomi, and A. Fujita, “A study on package stacking process for package-on-package (PoP),” in Proc. 56th Electron. Compon. Technol. Conf., San Diego, CA, pp. 6, May-June 2006.
[5] C.-C. Liu, S.-M. Chen, F.-W. Kuo, H.-N. Chen, E.-H. Yeh, C.-C. Hsieh, L.-H. Huang, M.-Y. Chiu, J. Yeh, T.-S. Lin, T.-J. Yeh, S.-Y. Hou, J.-P. Hung, J.-C. Lin, C.-P. Jou, C.-T. Wang, S.-P. Jeng, and D. Yu, “High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration,” in Proc. 2012 Int. Electron Devices Meeting, San Francisco, CA, pp. 14.1.1-14.1.4, Dec. 2012.
[6] K.-L. Wang, B.-Y. Lin, C.-W. Wu, M. Lee, H. Chen, H.-C. Lin, C.-N. Peng, and M.-J. Wang, “Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package,” IEEE Design & Test, vol. 34, no. 3, pp. 50-58, June 2017.
[7] L. Lin, T.-C. Yeh, J.-L. Wu, G. Lu, T.-F. Tsai, L. Chen, and A.-T. Xu, “Reliability characterization of chip-on-wafer-on-substrate (CoWoS) 3D IC integration technology,” in Proc. 2013 IEEE 63rd Electron. Compon. Technol. Conf., Las Vegas, NV, pp. 366-371, May 2013.
[8] B. Banijamali, C.-C. Chiu, C.-C. Hsieh, T.-S. Lin, C. Hu, S.-Y. Hou, S. Ramalingam, S.-P. Jeng, L. Madden, and D. Yu, “Reliability evaluation of a CoWoS-enabled 3D IC package,” in Proc. 2013 IEEE 63rd Electron. Compon. Technol. Conf., Las Vegas, NV, pp. 35-40, May 2013.
[9] T.-J. Chiu, Y.-C. Lin, Y.-C. Wang, C.-C. Wu, H.-C. Lin, and M.-J. Wang, “IPD robustness test methodology for InFO,” in Proc. e-Manufacturing and Design Collaboration Symposium (eMDC), pp.1-4, Sept. 2016.
[10] K. Zoschke, M. Jürgen Wolf, M. Topper, O. Ehrmann, T. Fritzsch, K. Kaletta, F.-J. Kaletta, and H. Reichl, “Fabrication of application specific integrated passive devices using wafer level packaging technologies,” IEEE Trans. Advanced Packaging, vol. 30, no. 3, pp. 359-368, Aug. 2007.
[11] M. Swaminathan, D. Chung, S. Grivet-Talocia, K. Bharath, V. Laddha, and J. Xie, “Designing and modeling for power integrity,” IEEE Transactions on Electromagnetic Compatibility, vol. 52, no. 2, pp. 288-310, May 2010.
[12] H. Johari, and F. Ayazi, “High-density embedded deep trench capacitors in silicon with enhanced breakdown voltage,” IEEE Transactions on Components and Packaging Technologies, vol. 32, no. 4, pp. 808-815, Dec. 2009.
[13] Y. Freeman, R. Hahn, P. Lessner, and J. Prymak, “Reliability and critical applications of tantalum capacitors,” in Proc. CARTS Europe 2007 Symposium, pp. 193-204, Oct. 2007.
[14] H. Chen, H.-C. Lin, and M.-J. Wang, “Smart GDBC Screening for High Quality IPD,” in Proc. e-Manufacturing & Design Collaboration Symposium (eMDC), pp. 1-4, Sept. 2018.
[15] H. Chen, M. Lee, L.-Y. Chen, and M.-J. Wang, “High Quality Test Methodology for Highly Reliable Devices,” in Proc. International Test Conference (ITC), pp. 1-6, Nov. 2019.
[16] Y.-C. Pan, Y.-R. Jian, H.-H. Liu, and C.-W. Wu, “A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices,” in Proc. VLSI Test Technology Workshop (VTTW), Nantou, Jul. 2018.
[17] AEC-Q001 Rev-D, Guidelines for Part Average Testing, AEC, Dec. 2011.
[18] M. J. Moreno-Lizaranzu, and F. Cuesta, “Improving electronic sensor reliability by robust outlier screening,” Sensors, vol. 13, no. 10, pp. 13521-13542, Oct. 2013.
[19] P. R. Pukite, and C. L. Berman, “Defect cluster analysis for wafer-scale integration,” IEEE Trans. Semiconductor Manufacturing, vol. 3, no. 3, pp. 128-135, Aug. 1990.
[20] A. D. Singh, and C. M. Krishna, “On optimizing VLSI testing for product quality using die-yield prediction,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 5, pp. 695-709, May 1993.
[21] A. D. Singh, P. Nigh, and C. M. Krishna, “Screening for known good die (KGD) based on defect clustering: an experimental study,” in Proc. International Test Conference (ITC), pp. 362-369, Nov. 1997.
[22] T. S. Barnett, A. D. Singh, and V. P. Nelson, “Burn-in failures and local region yield: an integrated field-reliability model,” in Proc. 19th IEEE VLSI Test Symposium (VTS 2001), pp. 326-332, April 2001.
[23] T. S. Barnett, A. D. Singh, M. Grady, and K. Purdy, “Yield-reliability modeling: experimental verification and application to burn-in reduction,” in Proc. 20th IEEE VLSI Test Symposium (VTS 2002), pp. 75-80, April 2002.
[24] T. S. Barnett, A. D. Singh, and V. P. Nelson, “Extending integrated-circuit yield-models to estimate early-life reliability,” IEEE Trans. Reliability, vol. 52, no. 3, pp. 296-300, Sept. 2003.
[25] T. S. Barnett, M. Grady, K. Purdy, and A. D. Singh, “Exploiting defect clustering for yield and reliability prediction,” IEE Proceedings-Computers and Digital Techniques, vol. 152, no. 3, pp. 407-413, May 2005.
[26] S. Ioffe, C. Szegedy, “Batch normalization: Accelerating deep network training by reducing internal covariate shift,” in Proc. Int. Conf. Mach. Learn., pp. 448-456, July 2015.
[27] N. Srivastava, G. Hinton, A. Krizhevsky, I. Sutskever, and R. Salakhutdinov, “Dropout: a simple way to prevent neural networks from overfitting,” The journal of machine learning research, vol. 15, no. 1, pp.1929-1958, Jan. 2014.
[28] D. P. Kingma, and J. L. Ba, “Adam: A method for stochastic optimization,” in Proc. Int. Conf. Learn. Represent., pp. 1-41, May 2015.
[29] M. Lin, Q. Chen, and S. Yan, “Network in network,” arXiv preprint arXiv:1312.4400, Dec. 2013.
[30] K. He, X. Zhang, S. Ren, and J. Sun, "Deep residual learning for image recognition", in Proc. IEEE Conference on ComputerVision and Pattern Recognition, pp. 770-778, June 2016.
[31] C. Szegedy, W. Liu, J. Yangqing, P. Sermanet, S. Reed, D. Anguelov, D. Erhan, V. Vanhoucke, and A. Rabinovich, “Going deeper with convolutions,” in Proc. 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), pp. 1-9, June 2015.
[32] Wikipedia. “Sensitivity and specificity” Last modified Aug. 24, 2020. https://en.wikipedia.org/wiki/Sensitivity_and_specificity.