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研究生： 卓偉漢
Cho, Wei-Han
論文名稱： 應用於無線通訊系統與光通訊系統接受器之前端放大器
Pre-Amplifiers for Wireless and Optical Receivers
指導教授： 徐碩鴻
Hsu, Shuo-Hung
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 65
中文關鍵詞： 低雜訊放大器 、雜訊最佳化 、雙閘極電晶體 、變壓器回授式匹配電路 、RGC電流緩衝器 、反向器式轉阻放大器 、高速轉阻放大器
外文關鍵詞： LNA, noise optimization, dual-gate transistor, transformer-feedback matching network, RGC current buffer, inverter-type TIA, high speed TIA
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    • In this thesis, five pre-amplifiers for communication systems are discussed regarding the design, simulation, and measurements. According to their applications, they can be separated into two wireless receiver pre-amplifiers and three optical receiver pre-amplifiers.
    For wireless receiver pre-amplifiers, an ultra-low-power 24 GHz low noise amplifier is implemented. By the noise optimization technique with MMIN as the design guideline, the ultra-low-power 24 GHz low noise amplifier attains a peak gain of 9.2 dB and minimum noise figure of 3.7 dB. Under 1V supply voltage, the circuit consumes only 2.78 mW. Another wireless receiver pre-amplifier, transformer-feedback dual-gate 24 GHz LNA, adopts the dual-gate transistors with gate-source transformer-feedback matching network and drain-source transformer-feedback matching network. It achieves a peak gain of 9.5 dB and a minimum noise figure of 4.7 dB. It is worth mentioning that under only 9.38 mW power consumption, the transformer-feedback dual-gate 24 GHz LNA exhibits excellent linearity of a -6 dBm P1dB and a 2.3 dBm IIP3.
    For optical receiver pre-amplifiers, by detailed analysis of the regulated cascode (RGC) current buffer and inverter-type TIA, a 7Gb/s low-power TIA with serial inductor peaking is implemented achieving a ZT of 51.4 dBΩ and a bandwidth of 4.6 GHz. In addition, a 5 Gb/s ultra-low-power inductorless TIA demonstrates a ZT of 56.5 dBΩ and a bandwidth of 3.0 GHz, and a 7.5 Gb/s low-power inductorless TIA attaining a ZT of 53.5 dBΩ and a bandwidth of 4.3 GHz.

    於此論文中，主要將探討五項通訊系統前端放大器之設計、模擬與量測，按照其應用可分為兩項無線通訊系統前端放大器與三項光通訊系統前端放大器。
    在無線通訊系統前端放大器方面，此論文完成一項超低功率24 GHz低雜訊放大器(An ultra-low-power 24 GHz low-noise amplifier)。藉由以MMIN為準則之雜訊最佳化方法，其達成功率增益(Power gain) 9.2 dB、雜訊指數(Noise Figure) 3.7 dB，並且在1 V的供應電壓低下功耗僅2.78 mW。另一項變壓器回授式雙閘極24 GHz低雜訊放大器(A transformer-feedback dual-gate 24 GHz LNA)則採用雙閘極電晶體搭配閘極源極變壓器回授式匹配電路與汲極源極變壓器回授式匹配電路，達成9.5 dB功率增益與4.7 dB雜訊指數。值得一提的是，在僅9.38 mW功耗底下，其P1dB與IIP3分別為-6 dBm與2.3 dBm，展現了相當優良的線性度。
    在光通訊系統前端放大器方面，藉由完整分析RGC(Regulated cascode)電流緩衝器與反向器式轉阻放大器(inverter-type TIA)，分別達成增益51.4 dBΩ與頻寬4.6 GHz之7 Gb/s低功率串聯電感轉阻放大器(7 Gb/s low-power TIA with serial inductor peaking)、增益56.5 dBΩ與頻寬3.0 GHz之5 Gb/s超低功率無電感轉阻放大器(5 Gb/s ultra-low-Power inductorless TIA)以及增益53.5 dBΩ與頻寬4.3 GHz之7.5 Gb/s低功率無電感轉阻放大器(7.5 Gb/s low-power inductorless TIA)。

    ABSTRACT ii 摘要 iii CONTENTS v LIST OF FIGURES vii Chapter 1 Ultra-Low-Power 24 GHz Low-Noise Amplifier 1 1.1 LNA in Wireless Receiver Frond-End 1 1.2 Design for Ultra-Low-Power 24 GHz LNA 3 1.2.1 The Principle of LNA Design 3 1.2.2 Noise Optimization Technique for Low-Power LNA 5 1.2.3 Power-Constrained Simultaneous Noise and Input Matching 12 1.3 Circuit Topology and Analysis 15 1.4 Simulation and Measurement Results 18 Chapter 2 Transformer-Feedback Dual-Gate 24 GHz Low-Noise Amplifier 21 2.1 Inductive Components in Integrated Circuit 21 2.2 Design for Transformer-Feedback Dual-Gate 24 GHz LNA 26 2.2.1 Dual-Gate NMOS in 0.18 μm CMOS technology 26 2.2.2 Gate-Source Transformer-Feedback Matching Network [15] 30 2.2.3 Drain-Source Transformer-Feedback Matching Network [16] 31 2.3 Circuit Topology and Analysis 34 2.4 Simulation and Measurement Results 36 Chapter 3 High Speed Low-Power Transimpedance Amplifiers 39 3.1 TIA for Optical Interconnect 39 3.2 Design for High Speed Low-Power TIAs 41 3.2.1 The Principle of TIA Design 41 3.2.2 Regulated Cascode Current Buffer 43 3.2.3 Inverter-Type TIA 47 3.3 7 Gb/s Low-Power TIA with Serial Inductor Peaking 48 3.3.1 Circuit Topology and Analysis 48 3.3.2 Simulation and Measurement Results 49 3.4 5 Gb/s Ultra-Low-Power Inductorless TIA 53 3.4.1 Circuit Topology and Analysis 53 3.4.2 Simulation and Measurement Results 54 3.5 7.5 Gb/s Low-Power Inductorless TIA 57 3.5.1 Circuit Topology and Analysis 57 3.5.2 Simulation and Measurement Results 59 References 63

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