本論文首先提出一個新穎之非晶矽薄膜電晶體結構，藉由改善具蝕刻終止層架構之非晶矽薄膜電晶體而達到比傳統非晶矽薄膜電晶體低數倍的低漏光電流之特性。另外因為受到非晶矽通道蝕刻製程的影響，使得導通電流稍微降低，在本文中對於降低的導通電流，我們也提供了可能的解釋機制。即使導通電流些微降低，新結構整體的最高導通電流與最低漏電流的比值仍遠大於傳統的非晶矽電晶體，這項特點使得此結構可以廣泛應用於高解析度及高亮度的液晶顯示面板，而由於其超低漏電流特性使其更可以應用於X光感應器等應用。
此外，我們將目前傳統雙閘極電晶體依據其特性不同歸類成兩種不同類型，歸類方式以上閘極 （透明電極）是否跨越汲極與源極為主，若將上閘極跨越汲極與源極歸類為A類，未跨越者為B類。A類雙閘電晶體的導通電流不太隨著上閘極透明電極的長度而變，且其漏電流遠大於單極電晶體以及B類電晶體，而B類電晶體則呈現與單極電晶體幾乎相同的漏電流，之所以如此可能是由於上閘極與汲極、源極間存在高阻抗區域使得電洞流不易在背通道傳導。在此我們亦發現A跟B類電晶體皆具有比傳統單極電晶體較低光漏電流的特性，我們在此也嘗試提供了一些解釋機制。由於傳統雙極電晶體雖然擁有高導通電流與低漏光電流特性，但是其所擁有較高的寄生電容（CGS）卻是一大缺點，較高寄生電容會使顯示面板呈現閃爍的效應（Flicker），在本文中也提供可能的寄生電容量測方法並利用模擬軟體來驗證量測方法的準確度。一種新型非對稱雙極電晶體在此提出用以解決傳統雙極電晶體的高寄生電容缺點，並且做成解析度160╳128, 114 dpi的高效能1.8吋面板用以與傳統面板比較差異性。
隨著GOA（Gate driver on array）電路的流行，高密度、高W/L的非晶矽薄膜電晶體研究受到重視。傳統的直流(DC)量測方式無法顯示出實際上電晶體在交流(AC)驅動時的特性。在本論文中，我們使用一種新型暫態量測系統來量測暫態內電晶體電流的特性，成功的量得暫態電流，同時也發現元件密度越高，W/L越大，使用傳統量測誤差也會越大。
非晶矽電晶體的穩定度一直是很重要的課題，在此簡單的提供常見的兩種機制來解釋臨界電壓的不穩定問題，並利用Stretched Exponential 模型來萃取一些重要元件的穩定度參數。另外利用研究非晶矽電容的正負偏壓穩定度測試來驗證缺陷在能帶上可能產生的位置，並驗證屬於懸吊鍵機制(defect creation)的缺陷產生是可逆的，可以藉由在大氣下加熱180℃後放置二十四小時候回復到電容初始狀況。本論文最後亦討論濕度與光對非晶矽元件的影響，相對濕度越高漏電流增加，為了驗證推測，我們利用雙極電晶體並在上閘極加了不同極性電壓，發現加正電壓後漏電效應與濕度增加的效應相同，故推測水分子在元件表面似乎扮演了正電荷的角色，能改變靠近背通道部分的能帶，使漏電增加。

In this thesis, we have introduced a new ESSC-TFT structure, which exhibits lower leakage current than that of conventional ES-TFT structure under back light illumination and dark environments, respectively. Although the on-currents may slightly be degraded by the etching process, the on/off current ratio under back light illumination environment is still much larger than the one in the conventional ES-TFT structure. We also provide a possible mechanism and methodology for the worse on-currents of the ESSC-TFTs. Such a new TFT device will enable high-resolution and high-brightness LCDs for next-generation applications; besides, the characteristics of lower leakage under dark environment also make ESSC-TFT device a suitable candidate for X-ray image-sensor applications.
Two types of dual-gate TFTs have shown the different electrical characteristics; the on-currents of type B TFTs are correlated to the lengths of ITO top gate. On the contrary, the type A devices nearly keep a certain quantity of on currents regardless of the size of ITO length. For the off state, the type A devices exhibit higher leakage currents than both type B devices and control samples, while the type B devices show almost the same leakage quantity with the control samples. This is due to the high impedance of intrinsic a-Si:H in the region between the ITO gate and source/drain contact. We also first observed that both type A and type B dual-gate TFTs show lower photo-leakage current than conventional TFTs and applied a proper mechanisms and explanation to this phenomenon. We also try to develop a measurement methodology to obtain the real TFT parasitic capacitance, and a simulation methodology is also introduced to verify our measurement results here. By using this measurement method, the conventional dual-gate TFTs are realized not suitable for LCD fabrication due to the inevitable increased CGS. The asymmetric dual-gate TFT is thereby introduced to overcome the shortcoming. High performance 1.8” asymmetric dual-gate TFT-LCDs with 114 dpi and 160×128 resolution are also demonstrated here.
A transient measurement method to estimate the real performance of a a-Si:H TFT in a GOA (Gate driver on array) circuits has been described. The conventional DC measurement is insufficient to be used to describe the AC driving behaviors of a a-Si:H TFT due to the long DC measurement time can heat up the device and obtain the inaccurate results for circuit simulations. In this thesis, we also found that Larger channel width, shorter channel length, smaller device area and higher driving bias can also enhance the self-heating effect in a-Si:H TFTs by transient measurements.
Two mechanisms of threshold voltage of the a-Si:H TFT metastability are introduced, and the stretched exponential model is used to extract the critical parameters of the defect creation. The point defect creation is proved to be reversible by the annealing process with a certain relaxation time by a series bias stress experiments tested on numbers of three-layer capacitors. The carrier trapping in insulator has also been observed with high voltage bias above 60V, which the capacitor cannot be recovered to its initial state. Furthermore, the humidity effect on a a-Si:H TFT has also been observed. The leakage current in a-Si:H TFTs increases exponentially and saturated at high relative humidity. This confirm that the leakage current in a-Si:H TFTs is strongly affected by the water molecules on the top passivation layer. The water molecules act as a positive charges as can be verified by the dual-gate a-Si:H TFT with various top gate biases. The leakage current of the a-Si:H TFTs with photo-illumination and humidity environment is also observed in this thesis.

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