本研究提出具低複雜度前景式校正與動態元件匹配功能的十位元1GS/s電流引導式數位類比轉換器，採用製程為TSMC 65 nm，1P9M互補金氧半導體。
在輸出負載為50Ω，雙端差動輸出訊號範圍1.6V下，靜態參數的表現上，DNL與INL皆在0.1LSB內；動態參數的表現上，輸入訊號在奈奎斯頻段內SFDR皆達75dB以上。
校正電路的部分利用SAR ADC作為前景式校正(foreground calibration)的誤差偵測器(error detector)。
轉換器正常運作模式下會根據電流誤差預先調整輸入訊號(LSB predistortion)來補償誤差，再配合亂數輪轉二進位權重(Random Rotated Binary Weighting)演算法來使非線性所引起的諧波失真轉換為與輸入訊號無關的隨機雜訊，綜合上述機制能達到高精準度之高速數位類比轉換器。

A 10 bit 1 GS/s digital to analog to digital converter with a Low Complexity Foreground Calibration and Dynamic Element Matching is presented, fabricated in a TSMC 65 nm process and 1P9M complementary MOSFETs.
The measured differential nonlinearity and integral nonlinearity are lower than 0.1 least significant bit(LSB) as well as the spurious free dynamic range(SFDR) measured is better than 75dB from DC to Nyquist while driving a 50Ω load with an output swing of 1. V_pp6.
This work takes successive approximation analog to digital converter(SAR ADC) as current error detector in foreground calibration circuit.
In normal mode, data converter will adjust input digital code to compensate the current error by LSB predistortion algorithm. Besides, we also take Random Rotated Binary Weighting Selection(RRBS) as DEM to disturb the correlation between current error and input frequency.
Above all, we can improve the harmonic distortion effectively and get a high SFDR performance.

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