以介面工程改善鐵電氧化鉿鋯記憶體之可靠度表現

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研究生：	彭皓楷 Peng, Hao-Kai
論文名稱：	以介面工程改善鐵電氧化鉿鋯記憶體之可靠度表現 Improved Reliability of Ferroelectric HfZrOx-based Memory With Interface Engineering
指導教授：	巫勇賢 Wu, Yung-Hsien
口試委員:	張廖貴術 Chang Liao, Kuei-Shu 吳永俊 Wu, Yung-Chun 荊鳳德 Chin, Albert 蘇俊榮 Su, Chun-Jung
學位類別：	博士 Doctor
系所名稱：	原子科學院 - 工程與系統科學系 Department of Engineering and System Science
論文出版年：	2023
畢業學年度：	111
語文別：	英文
論文頁數：	168
中文關鍵詞：	鐵電性、氧化鉿鋯、鐵電電容、鐵電電晶體、P型通道、極化電流峰分裂、一階反轉曲線、可靠度、多位元儲存、微波退火
外文關鍵詞：	Ferroelectricity, HfZrO, FeCap, FeFET, P-Channel, Switching Current Split-Up, FORC, Reliability, Multi-Level Cell, Microwave Annealing
相關次數：	點閱：2 下載：0
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鐵電記憶體由於具備寫入速度快和低消耗功率等特性，為前瞻性新興記憶體技術之一，有利於彌補現有記憶體階層中，高速DRAM 和非揮發性Flash之間的差異。近年來，CMOS製程相容之鐵電氧化鉿鋯(HfZrOx)已成功製作成鐵電電容器、鐵電穿隧接面以及鐵電電晶體等各種類型的鐵電記憶體以適合不同應用，非揮發性、出色的微縮能力和多位元儲存能力亦有利於作為高密度儲存。然而，反覆寫入-抹除後所產生的電荷捕捉效應將抵消這些優勢，造成寫入後讀取延遲增加以及記憶視窗降低。另外，鐵電電容器與鐵電電晶體在喚醒和子循環過程，鐵電疇去釘扎和釘扎亦會影響多位元儲存穩定性。
本論文首先著重研究高介電常數之氮氧化鋁介面層對鐵電電晶體性能影響，與採用二氧化矽介面層元件相比，由於氮氧化鋁具有較大的介電常數以及價帶位能差(valence band offset)，有助於提升鐵電電晶體之記憶視窗、資料維持性與耐久度。若進一步以氮氧化鋁介面層搭配鐵電層厚度微縮，可降低n通道與p通道鐵電電晶體記憶視窗差異，有利於實現記憶體內邏輯(logic-in-memory)相關應用。此外，具有氮氧化鋁介面層的p通道鐵電電晶體，在經過高累積輻射劑量照射後，仍可維持低寫入後讀取延遲能力，顯示此種結構的鐵電記憶體亦具有良好的抗輻射能力。接著，本論文亦探討鐵電電晶體操作在多位元儲存之可靠度表現，透過同時量測臨界電壓(threshold voltage)以及切換電流(switching current)，證實以氨氣電漿對矽基板表面進行預處理，可抑制鐵電電晶體操作在子循環後的局部釘扎效應。最後，我們提出一種可用於鍺鐵電電晶體的混合退火方案，透過微波退火搭配快速熱退火，大幅減少鍺基板與鐵電層介面之缺陷密度，使其不僅具有大記憶視窗可用於多位元儲存，亦改善了可靠度，為下世代鍺鐵電電晶體開創新契機。

Ferroelectric memory is one of the promising emerging memory technologies due to its fast write speed and low power consumption. It provides an opportunity to bridge the gap between high-speed DRAM and non-volatile Flash in the current memory hierarchy. In recent years, CMOS-compatible ferroelectric HfZrOx has been successfully integrated with various types of ferroelectric memories such as ferroelectric capacitor (FeCap), ferroelectric tunneling junction (FTJ), and ferroelectric FET (FeFET) for versatile applications. The non-volatile characteristic, excellent scalability, and multi-level cell (MLC) capability of these devices are beneficial for high-density storage. However, charge trapping, which can occur after repeatedly programming and erasing, counteracts these advantages. It not only increases the read-after-write latency but also degrades the memory window (MW). In addition, the MLC stability is associated with the domain de-pinning and pining during wake-up and sub-cycling for FeCap and FeFET.
This dissertation first focuses on the impact of the high-k AlON interfacial layer (IL) on the performance of FeFETs. Compared to SiO2 IL, AlON IL possesses a larger dielectric constant and valence band offset, which helps improve the memory window, data retention, and endurance of FeFETs. Using an AlON IL in combination with reduced ferroelectric layer thickness can further alleviate the MW discrepancy between n-channel and p-channel FeFETs, thereby facilitating logic-in-memory applications. In addition, p-channel FeFETs with AlON IL retain low read-after-write latency after being exposure to high radiation doses, indicating excellent radiation tolerance of this structure as well. Next, the MLC performance of FeFETs is also evaluated by simultaneously measuring the threshold voltage and switching current. It is confirmed that the Si surface with NH3 plasma treatment can suppress the local domain pinning of FeFETs after being subjected to sub-cycling. Finally, a novel hybrid annealing scheme is proposed for Ge-based FeFETs, which combines microwave annealing with rapid thermal annealing, to significantly reduce the defect density at the interface between Ge substrates and the ferroelectric layer. This not only enables large MW and MLC applications but also improves the reliability performance, which opens a new avenue for next-generation Ge-based FeFETs.

摘要    i
Abstract    ii
致謝    iv
Contents    vi
Figure Captions    x
Table Lists    xix
Chapter 1 Introduction    1
1-1 Brief Introduction of Ferroelectric Memory    1
1-1-1 Background    1
1-1-2 Doped-HfO2 Ferroelectric Memory    1
1-2 Realization of Truly Fast NVM    4
1-2-1 Write Speed Fluctuation    4
1-2-2 Read-After-Write Latency    5
1-3 Instability of MLC Operation    6
1-3-1 Charge Trapping Induced MW Degradation    7
1-3-2 Split-Up Effect Induced Instability    7
1-4 Organization of the Thesis    8
1-5 References    11
Chapter 2 Large Memory Window for FeFET Memory    22
2-1 Introduction    22
2-2 Experimental    24
2-3 Results and Discussion    25
2-3-1 Physical Analysis    25
2-3-2 Characterization of Ferroelectricity on Various IL    26
2-3-3 Impact of Various IL on MW of FeFETs    27
2-3-4 Impact of Various IL on Endurance Performance    27
2-3-5 Impact of Various IL on Retention Performance    30
2-4 Summary    31
2-5 References    32
Chapter 3 Symmetrical Memory Window Between n- and p-FeFETs    42
3-1 Introduction    42
3-2 Experimental    44
3-3 Results and Discussion    45
3-3-1 Memory Window for n- and p-FeFETs    45
3-3-2 Reliability Performance for n- and p-FeFETs    47
3-4 Summary    49
3-5 References    50
Chapter 4 Radiation Hardened FeFET with Improved Read Latency    58
4-1 Introduction    58
4-2 Experimental    60
4-3 Results and Discussion    60
4-4 Summary    65
4-5 References    65
Chapter 5 Enhanced Reliability of FeCap on Epitaxial Ge Film    73
5-1 Introduction    73
5-2 Experimental    75
5-3 Results and Discussion    76
5-3-1 Reliability and Physical Analyses of STD-based Devices    76
5-3-2 Reliability and Physical Analyses of AlON-based Devices    82
5-4 Summary    88
5-5 References    89
Chapter 6 Improved MLC Performance for BEOL Compatible FeCap    103
6-1 Introduction    103
6-2 Experimental    105
6-3 Results and Discussion    106
6-3-1 Impact of Processes on Ferroelectric Characteristics    106
6-3-2 Highly Reliable 3 Bits/Cell Operation for PDA-Stack    107
6-4 Summary    109
6-5 References    110
Chapter 7 Investigation of Sub-Cycling Induced Instability of FeFET    124
7-1 Introduction    124
7-2 Experimental    126
7-3 Results and Discussion    126
7-3-1 Basic Characteristics of HZO Layers    126
7-3-2 Impact of NH3 Treatment on Sub-Cycling Behavior    128
7-3-3 Multibit Capability of FeFET with NH3 Plasma Treatment    129
7-4 Summary    130
7-5 References    131
Chapter 8 Demonstration of MLC Capability on Ge FeFET Memory    145
8-1 Introduction    145
8-2 Experimental    146
8-3 Results and Discussion    148
8-3-1 Impact of Annealing Scheme on Properties of FE Film    148
8-3-2 Memory Performance, Reliability, and TLC Operation    149
8-4 Summary    151
8-5 References    152
Chapter 9 Conclusions and Recommendations    162
9-1 Conclusions    162
9-2 Recommendations    164
Publication List    166


                                

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Chapter 2
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Chapter3
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Chapter4
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Chapter5
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Chapter6
[6.1] Y. D. Lin, P. C. Yeh, Y. T. Tang, J. W. Su, H. Y. Yang, Y. H. Chen, C. P. Lin, P. S. Yeh, J. C. Chen, P. J. Tzeng, M. H. Lee, T. H. Hou, S. S. Sheu, W. C. Lo, and C. I. Wu, "Improving edge dead domain and endurance in scaled HfZrOx FeRAM," in 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 6.4.1-6.4.4.
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Chapter7
[7.1] V. Milo, G. Malavena, C. Monzio Compagnoni, and D. Ielmini, "Memristive and CMOS Devices for Neuromorphic Computing," Materials, vol. 13, no. 1, p. 166, 2020.
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[7.4] H. Mulaosmanovic, E. T. Breyer, T. Mikolajick, and S. Slesazeck, "Ferroelectric FETs with 20-nm-thick HfO2 layer for large memory window and high performance," IEEE Transactions on Electron Devices, vol. 66, no. 9, pp. 3828-3833, 2019.
[7.5] T. Ali, P. Polakowski, K. Kühnel, M. Czernohorsky, T. Kämpfe, M. Rudolph, B. Pätzold, D. Lehninger, F. Müller, R. Olivo, M. Lederer, R. Hoffmann, P. Steinke, K. Zimmermann, U. Mühle, K. Seidel, and J. Müller, "A multilevel FeFET memory device based on laminated HSO and HZO ferroelectric layers for high-density storage," in 2019 IEEE International Electron Devices Meeting (IEDM), 2019, pp. 28.7.1-28.7.4.
[7.6] C. Y. Liao, K. Y. Hsiang, F. C. Hsieh, S. H. Chiang, S. H. Chang, J. H. Liu, C. F. Lou, C. Y. Lin, T. C. Chen, C. S. Chang, and M. H. Lee, "Multibit ferroelectric FET based on nonidentical double HfZrO2 for high-density nonvolatile memory," IEEE Electron Device Letters, vol. 42, no. 4, pp. 617-620, 2021.
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[7.22] H. Zhou, J. Ocker, A. Padovani, M. Pesic, M. Trentzsch, S. Dünkel, H. Mulaosmanovic, S. Slesazeck, L. Larcher, S. Beyer, S. Müller, and T. Mikolajick, "Application and benefits of target programming algorithms for ferroelectric HfO2 transistors," in 2020 IEEE International Electron Devices Meeting (IEDM), 2020, pp. 18.6.1-18.6.4.

Chapter8
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[8.5] W. Chung, M. Si, and P. D. Ye, "First demonstration of Ge ferroelectric nanowire FET as synaptic device for online learning in neural network with high number of conductance state and Gmax/Gmin," in 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 15.2.1-15.2.4.
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[8.10] S. De, D. D. Lu, H. H. Le, S. Mazumder, Y. J. Lee, W. C. Tseng, B. H. Qiu, M. A. Baig, P. J. Sung, C. J. Su, C. T. Wu, W. F. Wu, W. K. Yeh, and Y. H. Wang, "Ultra-low power robust 3 bit/cell Hf0.5Zr0.5O2 ferroelectric FinFET with high endurance for advanced computing-in-memory technology," in 2021 Symposium on VLSI Technology, 2021, pp. 1-2.
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