隨著通訊市場的快速成長，人類已經進入了高速資料傳輸通訊系統的時代，
在這麼多的無線通訊應用像是手機或無線區域網路(wireless local area network，WLAN)之中，低成本且高積體化的 CMOS積體電路扮演著提升效統效能、加快電路操作速度、降低消耗功率與提供更複雜功能之關鍵性角色。然而，元件的縮小卻逐漸逼近了物理的極限，而使得摩爾定律（ Moore’s law）勢必在未來面臨挑戰，為此三維積體電路(three dimensional ICs)便成為良好的解決方案，透過矽穿孔的實現，堆疊晶片可以有效地縮短傳統二維電路間的內連接線，進而達到降低消耗功率與增加操作速度的需求。
而用來升頻或降頻的本地振盪器(local oscillator, LO)，是頻率合成器中鎖相迴路(phase locked loop, PLL)的心臟。因此本論文藉由二維及三維積體電路技術並著眼於其相關電路研究。首先，第二章我們進行了超低電壓之壓控振盪器(voltage controlled oscillator, VCO)設計，透過變壓器回授並加入閘極電感，此電路可以操作在小於 0.5 V的供給電壓並同時兼顧高可調範圍等優點，其可調範圍為目前已知之低電壓壓控振盪器當中最高的。
接著，在建立矽穿孔(through silicon via, TSV)等效電路模型之後，在第三章藉著矽穿孔疊接上下兩層晶圓，本論文提出一個可操作在 V頻段的壓控振盪器架構，其利用了三維積體電路中的矽穿孔來當作 LC共振腔中的電感。不僅具有雙頻帶操作的特性，其所占面積僅為傳統二維壓控振盪器的 1/10。
在第四章中本論文提出一個操作在 U頻段(f0= 50 GHz)使用雙導納交連耦合對之壓控振盪器，其不僅消耗較少功率(0.74 mW)，更可輕易地在 0.18 μm下操作於 U 頻段。
在第五章中本論文提出一個整數型(integer-N)鎖相迴路，基頻在 5.12 GHz的壓控振盪器(voltage controlled oscillator, VCO)經由電流模式邏輯(current mode logic, CML)除頻器與 TSPC (true single phase clock)除頻器除頻之後，再與輸入端所給之20 MHz 作相位比較，比較後的相位差經由電荷幫浦對電容充電或放電，並透過迴路濾波器來濾除高頻雜訊，所得之直流電壓用來當作可調電壓以調整振盪器的輸出頻率，最終鎖定在5.12 GHz，佈局前模擬(pre-layout simulation)的結果與理論相符合，期可做為將來設計的基礎與經驗。
最後，第六章為本篇論文做結論，並對將來提出一些建議。

With the rapid growth of the wireless communication market, mankind has entered the era of the high-speed data transmission. For so many wireless applications such as mobile phones and wireless local area network (WLAN), the CMOS integrated circuits with low cost and high integration level play an important role to improve the system performance, operating with increased speed, reduced power, and more complicated functions. However, scaling of device feature size is approaching the physical limitation, and the continuation of Moore’s Law becomes even questionable. A promising solution to this issue is the three-dimensional (3D) IC technology. By using the Through Silicon Vias (TSVs), the stacking dies can significantly shorten the interconnections in conventional 2D IC leading to reduced
power consumption and increased operation speed.
The local oscillator (LO), which converts either up or down the input frequency, is the heart of the phase-locked loop (PLL) in a frequency synthesizer. This thesis focuses on the related circuits in a PLL using both 2D and 3D IC technologies. First, the design of an ultra-low voltage VCO (voltage controlled oscillator) is presented in chapter II. By using the transformer feedback technique and adding the gate inductors, this circuit could operate at voltage less than 0.5 V and get the advantage of high tuning range at the same time. To the author’s best knowledge, the achieved tuning range is the highest compared to other reported low voltage VCOs.
Second, after establishing the equivalent circuit models of the TSVs (Through Silicon Vias), we proposes a V-band VCO configuration making use of the TSVs in 3D IC technology as the inductor in the LC tank, as shown in chapter III. The VCO allows dual-band operation, and only takes a chip area about 1/10 of the traditional 2D VCO.
In chapter IV, a U-band VCO (f0= 50 GHz) based on dual admittance transforming cross-coupled pair is presented in chapter IV, and the proposed VCO could operate at U band under very low power consumption (0.74 mW) even in 0.18
μm CMOS.
A integer-N PLL is presented in chapter V. Operating at 5.12 GHz, the fundamental frequency provided by the VCO is divided by the divider using current mode logic (CML) and divider in true single phase clock (TSPC), and then feedback
to the input to compare with the 20 MHz input frequency. The resulted phase difference then cause the charge pump to charge or discharge the capacitor. After filtering by the loop filter, the high frequency component is removed and the DC component is used as tuning voltage to change the frequency of VCO. Eventually it locks at the 5.12 GHz. The simulated results show that the pre-layout simulation is
consistent with the theory and could be expected to be the basis and experience of the future design.
Finally, chapter VI concludes this work and provides recommendation to the future work.

[1] B. Razavi, “Design of integrated circuits for optical communications,” McGraw-Hill, Sep. 2002.
[2] B. Razavi, “RF microelectronics,” Prentice-Hall, Nov. 1997.
[3] D. B. Lesson, “A simple model of feedback oscillator noise spectrum,” in Proc. IEEE, vol. 54, pp. 329-330, Feb. 1966.
[4] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179-194, Feb. 1998.
[5] D. Park and S. Cho, “An adaptive body-biased VCO with voltage-boosted switched tuning in 0.5-V supply,” in Proc. IEEE Eur. Solid-State Circuits Conference. (ESSCIRC), pp. 444-447, Sep. 2006.
[6] S. J. Jang, C. J. Huang, C. W. Hsue, and C. W. Chang, “A 0.3 V cross-coupled VCO using dynamic threshold MOSFET,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 3, pp. 166-168, Mar. 2010.
[7] K. Kwok and H. C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,” IEEE J. Solid-State Circuits, vol. 40, no.3, pp. 652-660, Mar. 2005.
[8] S. L. Jang and L. Chein-Feng, “A low voltage and power LC VCO implemented with dynamic threshold voltage MOSFETS,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 5, pp. 376-378, May 2007.
[9] F. Assaderaghi, S. Parke, D. Sinitsky, J. Bokor, P. K. Ko, and C. Hu, “Adynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation,” IEEE Electron Device Lett., vol. 15, no. 12, pp. 510–512, Dec. 1994.
[10]O. K. K., N. Park, and D. J. Yang, “1/f noise of NMOS and PMOS transistors and their implications to design of voltage controlled oscillators,” in Proc. IEEE Rad.
Freq. Integr. Circuits Symp., pp. 59-62, 2002.
[11]L. Jang, Y. H. Chuang, R. H. Yen, and S. H. Lee, “A 1.4 GHz CMOS extremely low voltage transformer-feedback VCO,” in Proc. CSTRWC’06, Macao, China, pp. 25–28, 2006.
[12]H. I. Lee, T. Y. Choi, S. Mohammadi, and L. P. B. Katehi, “An extremely low power 2 GHz CMOS LC VCO for wireless communication applications,” in Proc. Eur. Conf. Wireless Tech., pp. 41–44, 2005.
[13]E. S. A. Kytonaki and Y. Papananos, “A low voltage differentially tuned current adjusted 5.5-GHz quadrature VCO in 65-nm CMOS technology,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 5, pp. 254-258, May 2011.
[14]E. Beyne, “The rise of the 3rd dimension for system integration,” Interconnect Technology Conference, pp. 1-5, Jun. 2006.
[15]C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim,“High frequency electrical model of through wafer via for 3-D stacked chip packaging,” Electronics System-integration Technology Conference, vol. 1, pp. 215-220, Sep. 2006.
[16]D. Jang, C. Ryu, K. Lee, B. Cho, J. Kim, T. Oh, W. Lee, and J. Yu, “Development and evaluation of 3-D Sip with vertically interconnected through silicon vias (TSV),” Electronic Components and Technology Conference, pp. 847-852, 2007.
[17]C. Bermond, L. Cadix, A. Farcy, T. Lacrevaz, P. Leduc, B. Flechet, “High frequency characterization and modeling of high density TSV in 3D integrated circuits,” IEEE Workshop on Signal Propagation on Interconnects, 2009.
[18]C. Poh, D. Howard, P. C, D. Cressler, and J. Papapolymerou, “Pad de-embedding in RF CMOS,” in Asia-Pacific Microwave Conference Proceedings, 2010.
[19]J. Wang, T. Huang, Y. Wu, S. Hsu, Z. Lin, C. Lin, S. Sheu, T.Ku and C. Lin, “Testkey design of through silicon vias (TSVs) for accurate de-embedding and RF model parameters extraction,” International Conference on Solid State Devices and Materials, pp. 62-63, Nagoya, Sep. 2011.
[20]A. Tanabe and K. Hijioka, H. Nagase and Y. Hayashi “A novel variable inductor using a bridge circuit and its application to a 5-20 GHz tunable LC-VCO,“ IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 883-893, Apr. 2011.
[21]L. Li, P. Reynaert, and M. Steyaert, “A low power mm-wave oscillator using power matching techniques,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., pp. 469–472, Jun. 2009.
[22]C. Cao and K. O. Kenneth, “Millimeter-wave voltage-controlled oscillators in 0.13 um CMOS technology,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1297–1304, Jun. 2006.
[23]F. Vecchi, S. Bozzola,M. Pozzoni, D. Guermandi, E.Temporiti,M. Repossi, U. Decanis, A. Mazzanti, and F. Svelto, “A wideband mm-wave CMOS receiver for Gb/s communications employing interstage coupled resonators,” in IEEE Int. Solid-State Circuits Conf. Dig., pp. 220–221, Feb. 2010.
[24]C. Yu, W. Chen, C. Yu, and T. Lu, “A 60-GHz, 14% tuning range, multi-band VCO with a single variable inductor,” in IEEE Asian Solid-State Circuits Conf. Dig., pp. 129-132, Nov. 2008.
[25]K. Ishibashi, M. Motoyoshi, N. Kobayashi, and M. Fujishima, “76GHz CMOS voltage-controlled oscillator with 7% frequency tuning range,” in Symp. VLSI Circuit Dig. Tech. Papers, pp. 176-177, Jun. 2007.
[26]H. Hsieh, and L. Lu, “A V-band CMOS VCO with an admittance-transforming cross-coupled pair,” IEEE J. Solid-State Circuits, vol. 44, no.6, Jun. 2009.