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研究生: 陳友信
Chen, You-Shin
論文名稱: 一個使用CMOS影像感測器達到背景光消除的單片光學編碼器
A Monolithic Optical Encoder Using CMOS Image Sensor with Background Light Cancellation
指導教授: 謝志成
Hsieh, Chih-Cheng
口試委員: 邱進峯
Chiu, Chin-Fong
陳柏宏
Chen, Po-Hung
洪浩喬
Hong, Hao-Chiao
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 英文
論文頁數: 72
中文關鍵詞: 光學編碼器背景光消除增量式編碼器位置感測
外文關鍵詞: Optical Encoder, Background Light Cancellation, Incremental Encoder, Position Detection
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  • 本篇論文發表了一個使用CMOS影像感測器達到背景光消除的單片光學編碼器。在此晶片內實現了包含絕對式編碼器以及增量式編碼器兩種。絕對式編碼器是由42欄的像素電路以及可調雙閾值電壓量化器所組成。增量式編碼器則是使用了自行開發的共同中心交織排列光二極體陣列來感測四個互相相差90°弦波光訊號。為了達到更高的訊號雜訊比(SNR),因此當光強度越強時,用於避免電路飽和的背景光消除技巧是越必要的。所以我們提出了使用兩個感測反相訊號的光二極體串聯的方式來達到不需要增加額外電路便能消除背景光訊號的效果。在串聯的光二極體之後接續著的是全差動轉阻放大器,用於消除殘餘的背景光訊號,以達到共模雜訊消除並且把電流訊號轉變為電壓訊號的效果。接著一個可編程增益放大器則把全差動轉阻放大器的輸出訊號量放大至符合12-b SAR ADC的輸入範圍,並且也是作為全差動轉阻放大器與SAR ADC之間的電壓緩衝器。
    一個面積為1.4mm×1.65mm使用TSMC 0.18μm 1P6M CMOS標準製成所實現的光學編碼器讀出電路已經被實現且驗證。我們提出的使用串聯光二極體達到背景光消除的方式有效地消除了背景光電流還有從光源來的共模雜訊。全差動轉阻放大器的差動操作消除了殘餘的背景光訊號還有偶數諧波。因為使用了較少的讀出電路,訊號雜訊比可達到63dB。在週期為20μm的光柵下,最大的位移誤差僅有±0.22μm.


    This thesis presents a monolithic optical encoder using CMOS image sensor (CIS) with background light cancellation. Both absolute and incremental encoders are implemented in the chip with dual sensor arrays and the corresponding readout circuits. The absolute encoder is implemented using 42 columns of pixel with adjustable dual-threshold quantizer. The incremental encoder is implemented using the developed common-centroid interlacing (CCI) photodiode (PD) arrangement for the sensing of four quadrature sinusoidal signals dephasing 90° to each other. To achieve higher signal-to-noise ratio (SNR), the background light cancellation is necessary to prevent saturation with stronger light intensity. Thus, placing two opposite phases of photodiodes in series is proposed for background light cancellation without adding any extra circuit and therefore generates no extra noise. A fully differential transimpedance amplifier (FDTIA) is followed by the photodiodes to eliminate the residual signals, achieve the common-mode signal rejection and convert the differential currents into voltage signals. A programmable gain amplifier (PGA) is implemented to fit the input range of the following 12-b SAR ADC and serves as a voltage buffer between FDTIA and SAR ADC.
    A prototype of an optical encoder readout circuit has been fabricated in 0.18μm 1P6M CMOS standard technology with a chip area of 1.4mm×1.65mm. The background light cancellation using photodiodes in series is proposed, which effectively eliminates the background current and the common mode noise from the light signals. The differential operation of FDTIA cancels the residue background components and the even harmonics. Because of using fewer circuit devices, the SNR reaches 63dB. With a grating period of 20μm, the maximum error displacement is only 0.22μm.

    摘要 i ABSTRACT ii CONTENTS iii LIST OF FIGURES vi LIST OF TABLES ix Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Contribution 2 1.3 Thesis Organization 3 Chapter 2 Background Information 4 2.1 Operation of Optical Encoder 4 2.1.1 Moiré Effect 5 2.1.2 Incremental Encoder 6 2.1.3 Absolute Encoder 7 2.2 Fundamentals of Readout Circuit (ROIC) 8 2.2.1 Standard CMOS Compatible Photodiodes 9 2.2.2 Direct Injection (DI) 13 2.2.3 Buffered Direct Injection (BDI) 14 2.2.4 Gate Modulation Input (GMI) 15 2.2.5 Buffered Gate Modulation Input (BGMI) 15 2.2.6 Transimpedance Amplifier (TIA) 16 2.3 Review of Optical Incremental Encoder with Background Light Cancellation 22 2.3.1 Method I: Balanced Photoreceiver [4] 22 2.3.2 Method II: Differential Current Sensing [5] 23 2.4 Summary 25 Chapter 3 Proposed Low Noise Background Light Cancellation Technique 26 3.1 Block Diagram of the System 26 3.2 Background Light Cancellation Technique 28 3.2.1 Current-Mode Differential Sensing (CMDS) Frontend with Buffered Direct Injection (BDI) 29 3.2.2 Common-Centroid Interlacing (CCI) Photodiode (PD) Arrangement with Current-Mode Subtraction (CMS) 32 3.3 Summary 36 Chapter 4 Prototype Design of Optical Encoder Readout Circuit 37 4.1 System Architecture 37 4.2 Incremental Encoder 38 4.2.1 Fully Differential Transimpedance Amplifier (FDTIA) 38 4.2.2 Programmable Gain Amplifier (PGA) 42 4.2.3 Simulation Results of Incremental Encoder Readout Circuit 46 4.3 Absolute Encoder 47 4.3.1 Transimpedance Amplifier (TIA) 50 4.3.2 Comparator 52 4.3.3 Digital Control Circuit 53 4.4 Summary 55 Chapter 5 Measurement Results 56 5.1 Measurement Environment Setup 56 5.2 Chip Implementation 58 5.3 Incremental Encoder 59 5.3.1 Transfer Function 59 5.3.2 Phase Outputs and Displacement Error 60 5.3.3 Noise Measurement and SNR 62 5.3.4 Frequency Response 63 5.4 Absolute Encoder 64 5.4.1 Position Output 64 5.4.2 Offset Distribution 65 5.5 Summary 66 Chapter 6 Conclusions 68 6.1 Conclusion 68 6.2 Future Work 69 Bibliography 70

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