晶片功率估測可以在晶片設計過程中不同的層級來進行，在較低階層進行時(如電晶體層級或邏輯匣層級)，雖可得到較高的估測準確度，但往往需要很長的模擬時間；反之，在較高階層進行時(如暫存器階層或系統階層)，雖然可以得到很快的模擬速度，但估測的準確度往往不足。所以，傳統上，晶片的功率估測是很難做到又快又準。

在本篇論文中，我們將介紹三套功率評估軟體，並且建構了一個混合階層的功率評估系統。第一套軟體，稱為ToggleFinder，可以在暫存器階層對大型電路進行訊號變動的估測，並且由於過去的方法在針對大型電路估測時，常有兩個問題：第一，因未考慮到電路的行為可操作在多種不同的功能模式，而導致建立出來的功率模型不夠準確，為此，我們提出了多重模式的功率評估作法，來提高估測的準確度。第二，過去在建立功率模型的過程中，常使用線性迴歸的數學方法，在電路較大的情況，因需要較多的樣本數，所以需要較長的模型建立時間，我們提出了一個simulation-based linear approximation的方式，可提升此過程的效率。第二套軟體，稱為PowerBrick，可以自動化地對邏輯匣的標準元件庫以及記憶體產生器進行功率模型的建立，在此過程中，我們會執行較低階層的功率評估軟體，來得到較準確的功率結果。第三套軟體，稱為PowerMixer，進一步結合前兩套軟體，可以在邏輯匣層級或者暫存器層級進行功率的估測，同時我們也提出了在大型電路具有多重時脈域的情況下功率估測的作法。

此一混合階層的功率評估系統，結合了較低模擬層級的準確度與較高模擬層級的速度，使得整個功率評估過程可以又快又準。實驗結果顯示，此方法可以較傳統的邏輯匣層級模擬方式快約10倍，且估測的平均誤差在5%以內，有相當高的準確度。

Power estimation at the Register Transfer Level (RTL) often suffers from inadequate accuracy when applied to large designs, under realistic functional patterns. This problem is mainly due to the large variations of the switching activities induced in a circuit from one functional mode to another. We address this issue by a multi-mode methodology with two major enhancement techniques. Firstly, we use a power mode classification scheme to refine the power-consuming behaviors of a large design. Secondly, we incorporate a simulation-based linear approximation scheme for more efficient power characterization. The combination of these two techniques jointly contributes to higher accuracy. The proposed methodology has been realized as a practical tool that can fit into the commercial design flow. Experimental results of a number of real designs show that the estimation error can be reduced down to only 3.98 % on the average under realistic functional patterns.

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