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研究生： 涂竣傑
Chun-Chieh Tu
論文名稱： 內建自我速度評估電路與製程容忍的全數位鎖相迴路
Built-In Speed Grading with a Process-Tolerant All-Digital Phase-Locked Loop
指導教授： 黃錫瑜
Shi-Yu Huang
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2007
畢業學年度： 95
語文別： 中文
論文頁數： 47
中文關鍵詞： 內建 、自我速度評估 、製程容忍 、全數位鎖相迴路
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    • 速度的分類變的越來越重要，它可以幫助我們找出每一個晶片的效能。我們提出內建自我速度評估電路包含三個部份:第一個部分是把我們的待測電路包覆上內建自我測試電路。第二個部分是內建自我速度評估電路的控制器。第三部份是全數位鎖相迴路。全數位鎖相迴路就像是一個可調整的頻率產生器，它可以產生各式各樣不同的頻率在一個固定的振盪頻率範圍內，我們可以使用它來幫助我們找出待測電路在正常運作下的最快操作頻率。
    在我們提出的內建自我速度評估電路下，我們使用的全數位鎖相迴路是使用TSMC 0.18-um one-poly-six-metal CMOS的製成實現。它可以振盪出的頻率範圍為80MHz ~ 540MHz。它只需要196個參考週期就可以鎖定到我們想要的頻率。它的平均解析度為12ps，頻率鎖定誤差約為0.7%。鎖定誤差的計算公式是把全數位鎖相迴路鎖定到頻率的值與我們預期得到頻率的值作相減的動作之後再取絕對值，接下來除上我們預期得到頻率的值最後乘上 100%。輸出時脈的峰對峰時脈抖動小於69ps。
    為了防止製程變異造成的影響，我們提出二元-鄰近-線性的鎖定方法，這一個鎖定的演算法可以有效的幫助我們降低製程變異所造成的影響，提高鎖定的準確度，即使全數位鎖相迴路上的延遲閘有50%的延遲的變異，我們的頻率鎖定誤差只增加約1%左右。待測電路包覆上我們提出的內建自我速度評估電路只需要多增加2289個邏輯閘。

    Speed grading has becoming more and more important for nanometer technologies to support activities like process monitoring or performance diagnosis. In this work, we analyze the feasibility of providing such a capability through on-chip circuitry. This Built-In Speed Grading (BISG) methodology uses an All-Digital Phase-Locked Loop (ADPLL) as the programmable clock generator to provide various clock signals within a specific frequency range. The maximum operating speed of a circuit can thus be easily tracked down using a binary search process with multiple runs of built-in self-test.
    To accommodate larger process variation, we further explore a so-called binary-neighborhood-linear frequency-locking scheme for the underlying ADPLL, and thereby resulting in a higher accuracy. Experimental results show that only 2289 gates are adequate to provide this valuable infrastructure that may find numerous applications in IC testing and diagnostics.

    Contents Abstract…………………………………………………...……………02 Contents………………………………………………....……....……..06 List of Figures………………………………………………………….08 List of Tables…………………………………………..…………….....10 Chapter 1 Introduction…………………….……….....………………11 1.1 Motivation…………………………………………………..11 1.2 Thesis Organization…………………………………………13 Chapter 2 Built-In Speed Grading…………………………………….14 2.1 Preliminary……..……………….……………………………..14 2.2 The BISG Architecture………………………………….…….15 2.3 BISG Controller……………………………………………….18 Chapter 3 All-Digital Phase-Locked Loop………………….…………21 3.1 ADPLL Block Diagram..………………………………………21 3.2 Digitally Controlled Oscillator…….…………………………..23 3.3 Locking Algorithm….…….……………………………………26 Chapter 4 Experimental Results……..………………………………...29 4.1 Benchmark Circuit and ADPLL Characterization..……………29 4.2 Lock Error under Process Variation..………….…….…………32 4.3 Validation Environment…..........................................................34 4.4 Impact of Supply Voltage on Speed…………………………....35 4.5Verify BISG methodology by FPGA………………………….36 4.6 Area Overhead and Test Chip………………………………….38 4.7 Measurement…………………………………...........................39 Chapter 5 Conclusion…………………………………………………...44 Bibliography……………………………………………………………..45 List of Figures Fig. 2.1 Speed grading categories………………………………………..14 Fig. 2.2 Architecture of CUT with BISG………………………………..16 Fig. 2.3 An example of binary search…….……………………......……17 Fig. 2.4 The control and data signals of BISG…………………………..18 Fig. 2.5 State diagram of the BISG control flow..……………………….20 Fig. 3.1 Architecture of ADPLL..………………………………………..23 Fig. 3.2 Architecture of DCO..…………………………………………..24 Fig. 3.3 The coarse & fine tuning block in DCO…………………..…….25 Fig. 3.4 Coarse control code vs. output frequency of DCO……...………28 Fig. 4.1 The layout of a test chip…………………………………………31 Fig. 4.2 Lock error under delay variations……………………………….33 Fig. 4.3 Final speed range under different supply voltages……………....36 Fig. 4.4 The BISG flow (a)□(b)□(c) under CUT is fault free…................37 Fig. 4.5 The BISG flow (a)□(b)□(c)□(d) under CUT is faulty...………...38 Fig. 4.6 Area overhead of CUT with BISG……….……………………...39 Fig. 4.7 Die photo...............…………………………..…………………..40 Fig. 4.8 Measurement of BISG methodology….…………………………40 Fig. 4.9 Speed variations under various supply voltage.…………………42 Fig. 4.10 Input clock waveform of ATE…..…..……..…………………...42 Fig. 4.11 Shmoo plot of BISG……..…………………..…………………43 List of Tables Table 4.1 The summary of CUT’s with logic BIST…………..…………..30 Table 4.2 The characteristics of ADPLL……………………..…...………32 Table 4.3 Final speed range simulated by BISG…………….……………35 Table 4.4 Speed variations under various supply voltage…...…….……...41

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