透過摩爾定律 (Moore's Law)、超大積體電路 (Very-Large-Scale Integrated Circuit) 跨時代的演進，使得影像壓縮的領域朝向速度更快，體積更小並且同時支援多標準像是MPEG-1/2/4、H.264以及VC-1等SoC (System on Chip) 的晶片開發。MPEG-1/2/4、H.264以 及 VC-1 是很廣泛被應用的影像壓縮系統，在我的論文中就把MPEG4、 H.264、 VC-1以及最新的壓縮標準HEVC(H.265)整合在一起，有效率地實現出支援多標準的反餘弦轉換晶片。本篇論文提出了一種可以整合多種壓縮標準的架構來計算八點IDCT（反離散餘弦變換）的視頻編解碼器，共支援MPEG4，H.264/AVC，VC-1，和HEVC(今年一月國際電信聯盟（ITU）就已經正式批准通過了HEVC/H.265標準)。論文所提出的多標準硬體共用架構會比個別去實現更降低硬體成本，並確保計算過程中有共用到最多的電路，在設計上，只需要加法器和移位器就可以完成，不需要用到乘法器，大幅減低了係數運算中的重複片段，更利用此種共用特性得以建構低成本但支援多壓縮標準之轉換核心。。提出的方法不只讓架構只需加法器和移位器就可以完成，並用拆解係數的方法來進一步降低加法器的數目。因此，1-D轉換的核心只需要33（29+4）加法器和41（38+3）移位器，相較於乘法器來說要節省很多面積。最後，為了驗證，採用了TSMC 0.18的製程來實現這整合MPEG4，H.264/AVC，VC-1，和HEVC四種標準的晶片，其最高工作頻率是133.3 MHz，整體所用硬體的成本是19K。

The thesis presents a unified hybrid architecture to compute the 8-point IDCT (Inverse Discrete Cosine Transform) of multiple modern video codecs—MPEG4, H.264/AVC, VC-1, and HEVC (under development). The proposed hardware sharing architecture requires lower hardware cost than that of the individual implementations and ensures the maximum circuit reuse during the computation. The proposed architecture design needs only adders and shifters to reduce the hardware cost significantly. The proposed method can increase the circuit sharing capability and further reduce the number of adders. Hence, the proposed 1-D transform core only needs 33(29+4) adders and 41(38+3) shifters. For verification, a TSMC 0.18-μm process is applied to implement this chip, and the maximum operating frequency of the proposed design is 133.3 MHz with the hardware cost of 19K gates.

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