Rewiring is a well developed and widely used technique in the synthesis and optimization of traditional Boolean logic designs. The threshold logic is a new alternative logic representation to Boolean logic which poses a compactness characteristic of representation. Nowadays, with the advances in nanomaterials, research on multi-level synthesis, verification, and testing for threshold networks is flourishing. This paper presents an algorithm for rewiring in a threshold network. It works by rst removing a target wire, and then corrects circuit's functionality by adding a corresponding rectication network. It also proposes a simplication procedure for representing a threshold logic gate canonically, an important property of functional verication. The experimental results show that our approach enables the
logic restructuring of threshold logic networks. Additionally, our approach has 7.1 times speedup compared to the-state-of-the-art multi-level synthesis algorithm, in synthesizing a threshold network with a new fanin number constraint.

重接線已高度發展並廣泛地被運用在傳統布林邏輯設計上的合成與最佳化；臨界邏輯，相較於布林邏輯擁有較精簡的特性，是一種新的邏輯表示方式。現今，伴隨著奈米材料技術的演進，臨界邏輯上的研究，包含多層合成、驗證與測試，皆蓬勃發展。這篇論文提出了一個實作在臨界邏輯電路的重接線演算法，藉由移除一個目標線，並加上相對應的改正網路來修正電路的功能性；同時使一個臨界邏輯閘以標準型態表示的簡化程序也被提出，標準表示也是功能性驗證的一重要性質。實驗結果展現了此演算法實作在臨界邏輯電路上的邏輯重建能力；除此之外，在合成一個具有新輸入端數目限制的臨界網路，相較於最先進的臨界邏輯合成演算法，我們提出的方法加快了7.1倍的速度。

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