研究生: |
曹哲豪 Tsao, Che-Hao |
---|---|
論文名稱: |
Study of Staged Trap Generation and Spatial Trap Distribution in High-K Gated MOSFETs by Charge Pumping 應用電荷汲引技術於高介電係數閘極電晶體階段缺陷增生與空間之量測研究 |
指導教授: |
張廖貴術
Chang-Liao, Kuei-Shu |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
原子科學院 - 工程與系統科學系 Department of Engineering and System Science |
論文出版年: | 2010 |
畢業學年度: | 98 |
語文別: | 中文 |
論文頁數: | 102 |
中文關鍵詞: | 電荷汲引 、階段性缺陷增生 、空間缺陷分佈 |
外文關鍵詞: | Charge Pumping, Staged Trap Generation, Spatial Trap Distribution |
相關次數: | 點閱:1 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
為了滿足ITRS元件持續縮小化的要求,一般廣泛的認為高介電係數材料將取代原本的二氧化矽成為金氧半元件閘極介電層來改善漏電流的問題,然而在材料替換的過程中,許多問題產生,如電荷捕獲(charge trapping),臨界電壓(threshold voltage)飄移,載子遷移率下降(mobility degradation)等,因此應用在高介電係數閘極介電層電晶體的界面陷阱(interface traps)及氧化層陷阱(oxide traps)可靠度分析因應而生。
論文中第一部份介紹電荷汲引(charge pumping)技術量測方法。利用電荷汲引量測不同high-κ厚度介電層電晶體的界面陷阱密度與邊緣陷阱密度。描繪出陷阱空間中的分佈以及在矽能隙中能量的分佈情形。
接著透過分析CVS而產生的臨界電壓飄移隨時間的不同,可發現有缺陷捕捉(trapping)和電應力產生缺陷(stress-induced defects)的階段性區別。其中閘極氧化層缺陷(oxide trap)在臨界電壓的飄移佔了主要成分,所以因電應力而產生的陷阱也較嚴重。建議主要限制元件使用年限(life time)的原因也以改善閘極氧化層缺陷為優先。
在論文的最後一部分,應用空乏區和變頻的方法結合在電荷汲引技術上,可以用來量測在電晶體接面(junction)邊上三維陷阱密度的分布情形。利用上述的三維量測方法,對電晶體施加CVS和CHCS之可靠度使用條件進行分析。可發現隨所施加的電應力(stress)不同,在空間性上產生的陷阱密度分部情況也有很大的不同。期望在空間性上的瞭解為改善元件特性的製程方法提供方向。
For satisfy ITRS rule to keep device scale down. General method use high-kapa material which replaced silicon dioxide MOSFET to overcome gate leakage problem. But there are more issues in the process. Such as charge trapping, threshold voltage shift, mobility degradation, et al. Becasue of the problem mentioned, technique to detect interface traps and oxide traps be developed.
In the first part of thesis, introduce charge pumping technique. Use CP method to measure interface trap and border trap in different gate dielectric thickness MOSFET. To understand the trap energy distribution in silicon bandgap.
In the second part of thesis, experiment study the Constant-Voltage-Stress which shift threshold voltage in different time. The staged degredation can separate as trapping and stress-induced defects. After, experimental study discover oxide trap dominate the threshold voltage shift in trapping stage. And stress induced trap generation come from oxide trap are more serious. So, improve oxide trap in MOSFET would be first priority to satisfied life time restraint.
In the last part of thesis, experiment combine depletion region method and frequency method in Charge Pumping technique to measure device's junction side spatial distribution. And use this 3D distribution to detect trap generation after CHCS and PBTI reliability test. Experimental study discover the stress could be different spatial damaged in device. Wish using this knowledge help to improve device.
[1] K. Torii, Y. Shimamoto, S. Saito, O. Tonomura, M. Hiratani, Y. Manabe, M. Caymax, and J. W. Maes, "The mechanism of mobility degradation in MISFETs with Al2O3 gate dielectric," in Symp.VLSI Tech. Dig., 2002, pp. 188-189.
[2] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes and U. Schwalke, “Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics,” IEEE Electron Device Lett., vol. 24, pp. 87-89, 2003
[3] J. P. Han, E. M. Vogel, E. P. Gusev, C. D’Emic, C. A. Richter, D. W. Heh, and J. S. Suehle, "Energy Distribution of Interface Traps in High-K Gated MOSFETs," in Symp. VLSI Tech. Dig., 2003, pp. 161-162
[4] J. S. Bruglar and P. G. A. Jaspers, "Charge Pumping in MOS Devices",IEEE Transactions on Electron Devices, Vol.16, 1969, p.297
[5] Y. Maneglia and D. Bauza, "Extraction of slow trap concentration profiles in metal-oxide-semiconductor transistors using the charge pumping method,"J. Appl. Phys., vol. 79, pp. 4187–4192, 1996.
[6] S. Jakschik, A. Avellan, U. Schroeder, and J. W. Bartha, "Influence of Al2O3 dielectrics on the trap-depth profiles in MOS devices investigated by the charge-pumping method,"IEEE Trans. Electron Devices, vol. 51, pp.2252-2255, Dec. 2004.
[7] E.Y. Wu, A. Vayshenker, E. Nowak, J.Sune, R.-P.Vollerston, W.Lai, D.Harmon, "Experimental evidence of tBD power-law for voltage dependence of oxide breakdown in ultrathin gate oxides",IEEE Trans.On Electron Dev., vol.49, no.12, pp. 2244-2253, 2002.
[8] R. Degraeve et al., "Degradation and breakdown of 0.9nm EOT SiO2/ ALD HfO2/metal gate stacks under positive Constant Voltage Stress",IEDM Technical Digest., 2005
[9] S. Deora, et al., "A Comparative NBTI Study of HfO2, HfSiOx, and SiON p-MOSFETs Using UF-OTF I-DLIN Technique," Ieee Electron Device Letters, vol. 30, pp. 152-154, Feb 2009.
[10] E. N. Kumar, et al., "Material dependence of NBTI physical mechanism in silicon oxynitride (SiON) p-MOSFETs: A comprehensive study by ultra-fast on-the-fly (UF-OTF) I-DLIN technique," in 2007 Ieee International Electron Devices Meeting, Vols 1 and 2, ed New York: Ieee, 2007, pp. 809-812.
[11] D. Heh, et al., "Experimental evidence of the fast and slow charge trapping/detrapping processes in high-k dielectrics subjected to PBTI stress," Ieee Electron Device Letters, vol. 29, pp. 180-182, Feb 2008.
[12] P. J. McWhorter and P. S. Winokur, "Simple Technique for Separating the Effects of Interface Taps and Trapped-Oxide Charge in Metal-Oxide-Semiconductor Transistor", Applied Physics Letters, vol. 48, pp. 133-135, Jan 1986.
[13] G. Bersuker, et al., "Mechanism of electron trapping and characteristics of traps in HfO2 gate stacks," Ieee Transactions on Device and Materials Reliability, vol. 7, pp. 138-145, Mar 2007.
[14] D. Ielmini and F. Gattel, "Delay Correction for Accurate Extraction of Time Exponent and Activation Energy of NBTI," Ieee Electron Device Letters, vol. 30, pp. 684-686, Jun 2009.
[15] W. C. Wu, et al., "Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivation," in Ieee International Electron Devices Meeting 2008, Technical Digest, ed New York: Ieee, 2008, pp. 405-408.
[16] H. E. Maes and G. Groeseneken, "Determination of Spatial Surface-State Density Distribution in MOS and SIMOS Transistors After Channel Hot-Electron Injection," Electronics Letters, vol. 18, pp. 372-374, 1982.
[17] M. Tsuchiaki, et al., "A New Charge-Pumping Method for Determining The Spatial-Distribution of Hot-Carrier-Induced Fixed Charge in P-MOSFETS," Ieee Transactions on Electron Devices, vol. 40, pp. 1768-1779, Oct 1993.
[18] M. G. Ancona, et al., "Lateral Distribution of Hot-Carrier-Induced Interface Traps in MOSFET’," Ieee Transactions on Electron Devices, vol. 35, pp. 2221-2228, Dec 1988.
[19] M. Tsuchiaki, et al., "A New Charge Pumping Method for Determining the Spatial Distribution of Hot-Carrier-Induced Fixed Charge in p-MOSFET’s," Ieee Transactions on Electron Devices, vol. 40, pp. 1768-1779, Oct 1993.
[20] W. L. Chen, et al., "Lateral Profiling of Oxide Charge and Interface Near MOSFET Junctions Traps," Ieee Transactions on Electron Devices, vol. 40, pp. 187-196, Jan 1993.
[21] T. Aichinger and M. Nelhiebel, "Advanced Energetic and Lateral Sensitive Charge Pumping Profiling Methods for MOSFET Device Characterization-Analytical Discussion and Case Studies," Ieee Transactions on Device and Materials Reliability, vol. 8, pp. 509-518, Sep 2008.
[22] P. Masson, et al., "On the tunneling component of charge pumping current in ultrathin gate oxide MOSFET's," Ieee Electron Device Letters, vol. 20, pp. 92-94, Feb 1999.
[23] K. T. Lee, et al., "PBTI-associated high-temperature hot carrier degradation of nMOSFETs with metal-gate/high-k dielectrics," Ieee Electron Device Letters, vol. 29, pp. 389-391, Apr 2008.
[24] Y. Yasuda, et al., "Flicker-noise impact on scaling of mixed-signal CMOS with HfSiON," Ieee Transactions on Electron Devices, vol. 55, pp. 417-422, Jan 2008.
[25] Z. Y. Hsieh, et al., "Trend transformation of drain-current degradation under drain-avalanche hot-carrier stress for CLC n-TFTs," Microelectronics Reliability, vol. 49, pp. 892-896, Aug 2009.
[26] E. Amat, et al., "Competing Degradation Mechanisms in Short-Channel Transistors Under Channel Hot-Carrier Stress at Elevated Temperatures," Ieee Transactions on Device and Materials Reliability, vol. 9, pp. 454-458, Sep 2009.