由於現今語音訊號處理技術快速發展，傳統的訊號處理晶片已經無法滿足市場需求。本論文提出了基於現場可程式化邏輯閘陣列(FPGA)平台的麥克風陣列訊號處理系統，解決了數位訊號處理器(DSP)等晶片處理即時性差、暫存器資源少、不支援平行運算等缺點。本論文從理論研究、硬體設計、演算法三個方面對語音訊號處理的FPGA實現進行研究。硬體方面，應用麥克風陣列訊號處理的基礎理論設計並了均勻線性陣列與均勻環形陣列兩種麥克風陣列硬體架構；軟體程式方面，設計了硬體控制模塊及波束成形演算法：硬體控制模塊包含時脈除頻器、麥克風取樣模塊、USB傳輸模塊等；波束成形演算法涉及時間延遲相加(Delay and Sum, DAS)和最小方差無失真響應(Minimum Variance Distortionless Response, MVDR)兩種與其有限脈衝響應(FIR)濾波器的設計。最後將處理後的音訊透過相對轉移函數的方法求得其空間與強度的關係，並且與模擬的結果進行比較，藉此驗證此系統的效能。

Due to the fast development of speech signal processing technology nowadays, the traditional signal processing chips can no longer meet the market demand. This thesis proposes a microphone array signal processing system based on field programmable gate array (FPGA) platform, which eliminates some of the shortcomings of digital signal processor (DSP) such as processing speed, low register resources, and no support of parallel computing. This thesis describes in detail the FPGA implementation of array signal processing from the three perspectives: software and hardware design as well as the associated realization issues. In terms of hardware, two microphones geometries including a uniform linear array (ULA) and a uniform circular array (UCA) are employed in the design of the microphone arrays. Software, hardware control modules, and beamforming algorithms are developed. The hardware control modules include clock dividers, microphone sampling modules, USB transmission modules, etc. The beamforming algorithms including the Delay and Sum (DAS) and Minimum Variance Distortionless Response (MVDR) are implemented as finite impulse response (FIR) filters. Finally, the beampattern of the implemented array is experimentally validated via the relative transfer function (RTF).

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