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研究生: 林祐隆
You-Lung Lin
論文名稱: 電流密度限制下的離散型線寬調整
Discrete Wire Sizing under Current Density Constraints
指導教授: 王廷基
Ting-Chi Wang
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2006
畢業學年度: 94
語文別: 中文
論文頁數: 29
中文關鍵詞: 線寬調整電致遷移電流密度離散
外文關鍵詞: Wire Sizing, Electromigration, Current Density, Discrete
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  • 在此篇論文中,我們提出了一個在電流密度限制下的離散型線寬調整演算法。這個演算法有兩個步驟。第一個步驟先推導出一個連續的線寬函數使其線上任何位置之電流密度均相等並且滿足給定的電流密度限制。第二個步驟則是在不違反給定的電流密度限制下將連續的線寬函數轉成離散型的。關於第二個步驟,我們提出了三種時間複雜度都是線性的方法。第一個方法是簡單啟發式法,第二個方法是近似最佳法。以上的兩個方法都具有一個性質:在任何位置上離散型的線寬都不小於同位置的連續型線寬。最後一個方法在不考慮線的電阻時可證明出能獲得面積最小的離散型線寬。實驗顯示三種方法都相當快速,並且在三種方法中簡單啟發式法是最快的,而最佳法則花費最長的時間。此外,近似最佳法總是得到比簡單啟發式法來的好,然而仍稍差於最佳法得到的答案。


    In this thesis, we present an approach to discrete wire sizing subject to current density constraints. The approach contains two steps. The first step is to derive a continuous wire shape function in which every location of the wire has the same current density and satisfies the given current density constraint. The second step is to convert the continuous shape function into a discrete one without violating the given current density constraint, for which three linear-time methods are presented. The first one is a simple heuristic method, and the second one is near optimal. Both methods have the property that the wire width at any location is no less than the wire width of the given continuous wire sizing solution at the same location. The last method can be proved to obtain a discrete wire sizing solution of minimum area for the case without considering wire resistance. We conduct extensive experiments, and the results show that three methods are all very efficient, and among them, the simple heuristic method is the fastest one while the optimal method is the slowest one. Besides, the near optimal method is always able to generate a solution of smaller wire area than the simple heuristic method while it is slightly worse than the optimal method.

    ABSTRACT CONTENTS LIST OF FIGURES LIST OF TABLES Chapter 1 INTRODUCTION Chapter 2 PROBLEM FORMULATION Chapter 3 OUR APPROACH 3.1 Pre-processing step 3.2 A simple heuristic method 3.3 A near optimal method 3.4 An optimal method for the case without considering wire resistance 3.5 Inverse function derivations 3.5.1 Inverse function without considering wire resistance 3.5.2 Inverse function considering the wire resistance 3.6 Remarks Chapter 4 THEORETICAL RESULTS Chapter 5 EXPERIMENT RESULTS Chapter 6 CONCLUSIONS REFERENCES

    [1] C.-C. Teng, Y.-K. Cheng, E. Rosenbaum and S.–M. Kang, “Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects,” Proc. DAC, pp.752-757, 1996.
    [2] M. Shao, D. F. Wong , Y. Gao , L.-P. Yuan and H. Cao, “Shaping Interconnect for Uniform Current Density,” Proc. ICCAD, pp. 254-259, 2002.
    [3] K. Banerjee and A. Mehrotra, "Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets," Proc. ICCAD, pp. 158-164, 2001.
    [4] K. Hantanaka, T. Noguchi and K. Maeguchi, “A Generalized Lifetime Model for Electromigration under Pulsed DC/AC Stressing Conditions,” Proc. Symp. VLSI Technology, pp.19, 1990.
    [5] International Technology Roadmap for Semiconductors, 2002 Update.
    [6] J. Lienig , G. Jerke, “Current-Driven Wire Planning for Electromigration Avoidance in Analog Circuits” Proc. ASP-DAC, pp. 783-788, 2003

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