由於記憶體在系統單晶片中所佔的比例越來越大，根據ITRS的預測，在2010年之後記憶體在整個系統單晶片所佔的比例將達到90%以上，也就是說記憶體的良率將主宰整個晶片的良率；所以記憶體的失效分析和診斷在系統單晶片產品的生產與良率的提升中扮演了很關鍵的角色。
然而傳統的失效分析像是記憶體的實體電路分析通常是耗費時間且價格昂貴的；相較之下，以錯誤樣形為基礎的失效分析是比較能接受且簡單的，為了在新的製程或是新產品中能達到理想的良率，有賴於有效的自動化記憶體診斷與失效分析方法，並搭配使用備用記憶體的修復技術。
在我們的研究中，我們提出了一種以錯誤樣形為基礎的記憶體錯誤診斷之統計分析方法；為了能分析錯誤樣形，我們建立了一些工具—實體失效點陣印對圖轉換器與錯誤樣形擷取器，我們能用這些工具將由測試機台所得到的經壓縮的記憶體錯誤資料，搭配特定的規則將其轉換成失效點陣印對圖，而後從中擷取各種的錯誤樣形，在我們所建立的平台裡，在擷取錯誤樣形過程中，所有的錯誤樣形的參數可由使用者自行調整、定義，而且使用者也能自行定義特殊的錯誤樣形，以符合使用者的特殊需求，最後我們能得到所有的錯誤樣形的統計與錯誤樣形相關的資訊像是錯誤樣形在晶元上分佈的情況，或是錯誤樣形中錯誤的單元數目等等，最後我們也將我們的方法運用在業界的產品上，而結果是合理的。
我們所提出的以錯誤樣形為基礎的記憶體錯誤診斷統計分析的方法能幫助我們建立出一個實際錯誤發生的環境，提供詳盡的錯誤樣形的統計與其他有關錯誤樣形的資訊，這些資訊可以幫助我們用在晶元層級的分析，且能有效的幫助備用記憶體分析和備用記憶體元件的建立。

According to the recent ITRS report, memory cores will occupy more than 90% of the chip area
in just a few years. The design of embedded memory test has became an essential part of SOC
development infrastructure. Failure analysis (FA) and memory diagnostics play important roles in
SOC product development and yield ramp up. Conventional FA, like physical analysis, is timeconsuming
and expensive. Compared with physical analysis, the analysis based on failure pattern
is more acceptable and simple. To improve yield in new process flow, we need an efficient and
automatic methodology such as repair technique with redundant element or memory diagnostics.
In this thesis, we propose a failure pattern oriented memory diagnostics methodology based on
failure pattern statistics.
In order to analyze the failure patterns, we developed some tools—physical bitmap convertor
and failure pattern extractor (FPE)–help to convert bitmaps and extract failure patterns. We can
verify the result with the failure pattern viewer that was developed by our laboratory previously,
and we can identify the failure pattern which is special or appear frequently. The FPE provides the
failure pattern statistics and sufficient failure information such as the faulty cell count of each bit
line (BL) failure pattern, and the distribution of failure pattern after execution. This information
is helpful for redundant element and repair circuit design. This complete, detailed information is
also useful in the Redundancy Analysis (RA). In addition, we can use the failure pattern to narrow
down the potential cause of failures and identify possible defects with the defect dictionary on
wafer level. An experiment has been done on an industrial case, and the demonstrated results are
reasonable.
Our proposed approach provides another efficient way for memory diagnostics, and constructs
a model of realistic failure distribution. This information of realistic failure distribution can help us
to point out the key reason of the yield loss efficiently. The information of failure pattern generated
can be used to diagnose memory on wafer level. This work has been very helpful in redundancy analysis and memory diagnostics during memory product and yield improvement.

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