隨著可攜式電子產品之輕薄化及高效能需求，進行系統晶片整合以縮小構裝結構尺寸乃必然的趨勢。然而可攜式電子產品常因運送或使用不慎掉落而遭受劇烈衝擊，而造成內部結構的破壞，因此如何增強其抗衝擊能力已成為研發先進構裝之重要課題。
三維晶片對晶片堆疊構裝（3D Chip-on-Chip Stacking Package）不僅可有效使產品結構微小化，接點間距大幅縮小，且可增進電訊傳輸效率，故廣受各界重視。本論文即在利用數值模擬方法與實驗探討工研院所開發之一超細間距三維晶片對晶片堆疊構裝遭受掉落衝擊時之可靠度。此構裝主要由上晶片、下晶片及3,216個銅/鎳/錫銀（Cu/Ni/SnAg）I/O微接點（Micro Bump）所構成，因微接點間距及尺寸均遠小於傳統構裝，故其抗掉落衝擊尤應予重視。
本論文掉落衝擊測試係依據JEDEC（Joint Electron Device Engineering Council）規範進行，掉落衝擊測試機掉落平台自由落下時，產生一近似半弦波之加速度函數，最大加速度為1,500 G，脈衝時間為0.5毫秒。在數值模擬上，本論文則利用LS-DYNA® 有限單元套裝軟體建立一精確可靠之三維有限單元分析模型。為能準確模擬微接點在動態負載下之行為，本論文採用Johnson-Cook本構材料模式（Constitutive Model），以納入應變率及溫度之效應，而動態負載則藉由加速度輸入法（Input-G Method）進行模擬。三維有限單元分析模型計算求得之結果與實驗結果相較頗為脗合。
為評估微接點之疲勞壽命，本論文進而有系統地進行多次不同測試條件下之衝擊疲勞實驗，且經由光學顯微鏡檢測發現，微接點之破壞均發生於錫銀銲材部份。以此疲勞實驗結果為基礎，配合經由有限單元分析獲得之微接點錫銀銲材應變能密度，本論文成功建立了Darveaux 疲勞壽命預估方程式。最後，本論文以所建立之Darveaux疲勞壽命預估方程式對不同的錫銀銲材、填充底膠、介金屬厚度比例及上下晶片厚度等進行參數化分析，以供三維晶片對晶片構裝提升抗衝擊疲勞壽命能力之參考。

With the eager demand of light, thin, and high performance of portable electronic devices, it has been a trend for miniaturizing the structure packaging to integrate the system chip. However, the interior structure of the portable electronic devices could be destroyed as the portable electronics devices are subjected to severe impact due to the conveyance and careless drop. Therefore, it becomes an important issue for the development of advanced packaging to enhance the drop impact resistance of devices.
The three-dimensional (3D) Chip-on-Chip (CoC) Stacking Package receives great attention because of its ability to miniaturize the package, to significantly shorten the interconnect pitch, and to enhance electronic signal transmission efficiency. By the numerical simulation method and the experimental validation, this work aims to study the drop impact reliability of the ultra-fine-pitch 3D CoC Stacking Package which is developed by ITRI. This package consists of a top chip, a bottom chip and 3,216 Cu/Ni/SnAg I/O micro bumps. Because the pitch and size of micro bumps are much smaller than conventional package, it is crucial to pay more attention to its drop impact reliability.
The standard JEDEC（Joint Electron Device Engineering Council) specification is adopted in the drop impact test. As the drop table of drop impact tester freely falls, it produces an almost half-sine wave acceleration function, and its peak acceleration and impulse time are 1,500G and 0.5 ms respectively. As for the numerical simulation, the LS-DYNA finite element software is applied to create an accurate and reliable 3D finite element analysis model. To well simulate the dynamic responses of the micro bumps, a Johnson-Cook constitutive model, which takes into account the effects of strain rate and temperature, is employed, and the input-G method is applied for simulating the dynamic loading. The calculated results of 3D FE modeling match very well with the experimental data.
To evaluate the drop impact fatigue life of the micro bump, this work further systematically carries out a set of drop impact fatigue life experiments under different drop test conditions. Besides, through the optical microscope inspection, it is found that the failure area of micro bumps all occur at the SnAg zone. Based on the obtained fatigue test data and the strain energy density of SnAg of micro bump computed through FE analysis, a Darveaux drop impact fatigue life prediction equation is successfully constructed in this work. Finally, to provide a reference for promoting the drop impact fatigue life resistance for 3D CoC Stacking Package, the effects of different SnAg solders, underfill, IMC thickness ratio and the thickness of the top and bottom chip are investigated through the parametric study.

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