在協作三維晶片設計環境下用差模信號實現本地容錯穿矽連接孔

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研究生：	温景怡 Wen, Ching-Yi
論文名稱：	在協作三維晶片設計環境下用差模信號實現本地容錯穿矽連接孔 Localized Fault-Tolerant TSVs using Differential Signaling For Cooperative 3D-IC Design Environment
指導教授：	黃錫瑜 Huang, Shi-Yu
口試委員:	李昆忠 Lee, Kuen-Jong 李進福 Li, Jin-Fu 黃宗柱 Huang, Tsung-Chu
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2023
畢業學年度：	112
語文別：	英文
論文頁數：	41
中文關鍵詞：	穿矽連接孔
外文關鍵詞：	TSVs
相關次數：	點閱：40 下載：0
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一個有故障的穿矽連接孔（TSV）可能會損壞三維晶片，導致巨大損失，因為若是穿矽連接孔有錯，則必須將整顆已經黏合在一起的潛在昂貴的已知良好晶片丟棄。本篇論文提出了一個容錯穿矽連接孔方案，以避免這種災難性情況發生。我們的方法為將每個二進制信號使用兩個差模穿矽連接孔做傳輸。與先前的容錯穿矽連接孔方案相比，我們的測試和修復方案不僅是即時的，而且更加簡化，不需要全局測試結果分析和複雜的重構過程，因此特別適用於合作的多供應商三維晶片設計環境。

A faulty Through-Silicon Via (TSV) can potentially damage a three-dimensional chip, resulting in significant losses. If a TSV is faulty, the entire bonded stack of potentially expensive known-good dies must be discarded. This thesis proposes a fault-tolerant TSV scheme to prevent such catastrophic occurrences. Our approach involves using two differential TSVs for transmitting each binary signal. In comparison to previous fault-tolerant TSV schemes, our test and repair scheme is not only instant but much more simplified, needing no global test result analysis and complex reconfiguration process, thereby making it especially suitable for a cooperative multi-vendor 3D-IC design environment.

Abstract--------------------------------------------------i
摘要------------------------------------------------------ii
誌謝------------------------------------------------------iii
Content---------------------------------------------------iv
List of Figures-------------------------------------------vi
List of Tables--------------------------------------------viii
Chapter 1 Introduction------------------------------------1
1.1 Introduction------------------------------------------1
1.2 Thesis Organization-----------------------------------4
Chapter 2 Preliminaries-----------------------------------5
2.1 Delay Test Method-------------------------------------6
2.2 An Exemplar TSV Repair Scheme-------------------------7
2.3 Comparison of TSV Repair Methods----------------------8
2.4 Assumption of Our Differential TSV Pair---------------10
Chapter 3 Proposed Fault-Tolerant TSV Scheme--------------11
3.1 Basic Differential TSV pair---------------------------11
3.2 Dual-Railed Sensor Cell-------------------------------15
3.3 Complete Test-and-Repair Wrapper----------------------18
3.4 Fault Tolerant Sensor Cell----------------------------19
3.5 Coping Strategy for Bridging Faults-------------------22
3.6 Instant Test and Repair Flow--------------------------24
Chapter 4 Simulation Results------------------------------27
4.1 Layout and Area Overhead------------------------------27
4.2 Circuit Model for Simulation--------------------------30
4.3 Fault-Free Performance--------------------------------30
4.4 Analysis of Stuck-At Fault----------------------------31
4.5 Performance Analysis for Resistive Open Faults--------31
4.6 Performance Analysis for Leakage Faults---------------32
4.7 Performance Analysis for Bridging Faults--------------33
4.8 Performance Summary-----------------------------------35
Chapter 5 Conclusion--------------------------------------37
References------------------------------------------------38

                                

[1] I. Loi, S. Mitra, T. Lee, S. Fujita, and L. Benini, “A Low-Overhead Fault Tolerance Scheme for TSV-based 3D Network on Chip Links,” Proc. of Int’l Conf. on Computer-Aided Design, pp. 598 –602, Nov. 2008.
[2] U. Kang, H. Chung, S. Heo, D. Park, H. Lee, J. Kim, S. Ahn, S. Cha, J. Ahn, D. Kwon, et al., “8 GB 3-D DDR3DRAM using Through-Silicon-Via Technology,” IEEE Journal of Solid-State Circuits, Vol. 45, No. 1, pp. 111–119, 2010.
[3] A. Hsieh, T. Hwang, M. Chang, M. Tsai, C. Tseng, and H.-C. Li, “TSV redundancy: Architecture and Design Issues in 3D-IC,” Proc. of IEEE Design, Automation, and Test in Europe, pp. 166-171, March 2010.
[4] Y.-J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A built-in self-test scheme for the post-bond test of TSVs in 3D ICs,” Proc. of VLSI Test Symp, pp. 20–25, May 2011.
[5] Y.-J. Huang and J.-F. Li, “Built-In Self-Repair Scheme for the TSVs in 3-D ICs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 10, pp. 1600–1613, 2012.
[6] T.-C. Huang, “Cluster Error Correction and On-Line Repair for Real-Time TSV Array,” Proc of Asia Symp. on Quality Electronic Design (ASQED), Sep. 2015.
[7] L. Jiang, Q. Xu, and B. Eklow, “On Effective TSV Repair for 3D-Stacked ICs,” Proc. of IEEE Design, Automation, and Test in Europe, pp. 6–11, 2012.
[8] M. Nicolaidis, V. Pasca, and L. Anghel, “Through-Silicon-Via Built-In Self-Repair for Aggressive 3D integration,” Proc. of IEEE Int’l On-Line Testing Symp. (IOLTS), pp. 91–96, 2012.

[9] C.-C. Chi, C.-We. Wu, M.-J. Wang, H.-C. Lin, “3D-IC TSV Test, Diagnosis, and Repair,” Proc. of VLSI Test Symp., pp. 1-6, 2013.
[10] L. Jiang, F. Ye, Q. Xu, K. Chakrabarty, and B. Eklow, "On Effective and Efficient In-Field TSV Repair for Stacked 3D-ICs," Proc. of Design Automation Conf., pp. 1-6, 2013.
[11] W.-H. Hsu, M. A. Kochte and K.-J. Lee, "3D-IC test architecture for TSVs with different impact ranges of crosstalk faults", Proc. of Int’l Symp. on VLSI Design. Automation and Test (VLSI-DAT), pp. 1-4, Apr. 2016.
[12] S.-Y. Huang, M.-T. Tsai, Z.-F. Zeng, K.-H. Tsai, and W.-T. Cheng, "General Timing-Aware Built-In Self-Repair for Die-to-Die TSVs," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No 11, pp. 1836-1846, Nov. 2015.
[13] Y. Zhao, S. Khursheed, and B. M. Al-Hashimi, “Online Fault Tolerance Technique for TSV-Based 3-D-IC”, IEEE Trans. on VLSI Systems, Vol. 23, No. 8, Aug. 2015.
[14] L.-C. Li, W.-H. Hsu, K.-J. Lee and C.-L. Hsu, "An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST", Proc. of Asia and South Pacific Design Automation Conf., pp. 520-525, Jan. 2015.
[15] S. Wang, M. B. Tahoori, K. Chakrabarty, “Thermal-Aware TSV Repair for Electromigration in 3D ICs”, Proc. of Design Automation & Test in Europe Conf. (DATE), pp. 1291-1296, 2016.
[16] R. P. Reddy, A. Acharyya, and S. Khursheed, “A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs”, IEEE Trans. on VLSI Systems, Vol. 25, No. 7, July. 2017.
[17] S. Chen, Q. Xu, and B. Yu, “Adaptive 3D-IC TSV Fault Tolerance Structure Generation”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, No. 5, May 2019.
[18] Q. Wang, Z. Liu, J. Jiang, N. Jing, and W. Sheng, “A New Cellular-Based Redundant TSV Structure for Clustered Faults”, IEEE Trans. on VLSI Systems, Vol. 27, No. 2, Feb. 2019.
[19] D.-K. Maity, S.-K. Roy, and C. Giri, “Built-In Self-Repair for Manufacturing and Runtime TSV Defects in 3D ICs”, Proc. of IEEE International Test Conference India (ITC India), Aug. 2020.
[20] T.-C. Huang, "High-performance built-in self-routing for through-silicon vias", Electronics Letters, vol. 48, no. 9, pp. 480-482, 2012.
[21] M. F. Chen, C. S. Lin, E. B. Liao, W. C. Chiou, C. C. Kuo, C. C. Hu, C. H. Tsai, C. T. Wang, and D. C. H. Yu, “SoIC for Low-Temperature, Multi-Layer 3D Memory Integration”, Proc. of IEEE Electronic Components and Technology Conf., pp. 855-860, 2020.
[22] S. W. Liang, G. Wu, K. C. Yee, C. T. Wang, J.-J. Cui, and D. C. H. Yu, “High-Performance and Energy Efficient Computing with Advanced SoIC Scaling”, Proc. of IEEE Electronic Components and Technology Conf., pp. 1090-1094, 2022.
[23] S.-Y. Huang, J.-Y. Lee, K.-H. Tsai, and W.-T. Cheng, “At-Speed BIST for Interposer Wires Supporting On-the-Spot Diagnosis,” Proc. of Int’l On-Line Test Symp., June 2013.
[24] S.-Y. Huang, J.-Y. Lee, K.-H. Tsai, and W.-T. Cheng, “Pulse-Vanishing Test for Interposers Wires in 2.5-D IC,” IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD), Vol. 33, No. 8, Aug. 2014.
[25] P. R. O’Brien and T. L. Savarino, “Modeling the Driving-Point Characteristic of Resistive TSV for Accurate Delay Estimation,” Proc. of Design Automation Conf., pp. 512–515, Nov. 1989.
[26] L. Heller, W. Griffin, J. Davis, and N. Thoma, “Cascode Voltage Switch Logic: A Differential CMOS Logic Family”, Proc. of Int’l Solid-State Circuits Conf., pp. 16-17, 1984.
[27] “CIC Reference Flow for Cell-based IC Design”, Chip Implementation Center, CIC, Taiwan, Document no. CIC-DSD-RD-08-01, 2008.
[28] Y. Yu, Z. Yang, and K. Xu, “A Post-Bond TSVs Test Solution for Leakage Fault”, Proc. of IEEE Int’l Test Conf. in Asia (ITC-Asia), Oct. 2019.

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