30 Gbps負載平衡式布可夫-范紐曼交換機之設計與實作

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研究生：	張竣傑
論文名稱：	30 Gbps負載平衡式布可夫-范紐曼交換機之設計與實作 Design and Implementation of 30 Gbps Load-Balanced Birkhoff-von Neumann Switches
指導教授：	馮開明
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 通訊工程研究所 Communications Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	56
中文關鍵詞：	布可夫-范紐曼交換機
相關次數：	點閱：2 下載：0
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在此篇論文中，我們用的是負載平衡式布可夫-范紐曼交換機的架構。記憶體存取速度在製作高速網路交換機時是一個很重要的問題，但隨著網路頻寬的需求量大增，記憶體存取速度將無法滿足高速交換機的需求，因此，具有平行讀取與寫入的輸入佇列式交換機逐漸受到重視。此架構即是輸入佇列式交換機之一種，它可利用遞迴建構的方式擴充成N × N並擁有超高資料處理量與100%使用率的交換機。
論文中，總共有三種建立在此架構基礎上的交換機。第一個是應用在乙太網路且擁有序列輸出入阜與8/10B編/解碼器的8 × 8分時多工交換機，裡頭建立了三種模式，分別是編/解碼器驅動模式，編/解碼器旁路模式，與內建自我測試電路模式。第2個是利用超高速介面架構的平行列輸出入阜與8/10B編/解碼器的8 × 8分時多工交換機，還有一個修改過並擁有更大資料處理量的架構也列在其中。此更新的架構中也分為兩種模式，一個是8 × 8模式，另一個是自我測試電路模式。最後一個是雙模式的平行列輸出入阜8 × 8或是序列式輸出入阜64 × 64的分時多工交換機，內部自我測試的電路也包括在其中。以上所有架構都是採用0.18 CMOS的製程。
在各個架構各個章節中，所有的詳細設計流程都包含在內，如整體架構的介紹，內部各個電路架構的介紹，模擬環境的參數設定，使用的軟體，模擬結果，晶片的佈局與報告與實際晶片測試結果，最後，將對整體系統來做探討與改進。

The proposed load-balanced Birkhoff-von Neumann switch can achieve ultra high speed switch capability with N × N TDM switch via recursive construction. In this thesis, three architectures were implemented. The first one was an 8 × 8 TDM switch with serial input/output ports and embedded 8/10B CODEC for Ethernet applications. The second one was an 8 × 8 TDM switch with parallel input/output ports and embedded 8/10B CODEC using high speed interface. Another modified architecture is also included. The last was a dual-mode parallel 8 × 8 or serial 64 × 64 TDM switch for high speed networking application. A novel testing circuit was also implemented to easily verify switching results. All implementation were based on the 0.18 µm CMOS technology.

Chinese Abstract...........................................i
English Abstract......................................... ii
Acknowledgments......................................... iii
Contents..................................................iv

CHAPTER 1    Introduction                                 1
1    Current development of related research..............................................1
2 Load-balanced Birkhoff-von Neumann switch ...............................................3

CHAPTER 2 An 8 × 8 TDM switch with serial I/O ports IC     7
1 Overall architecture..........................................7
2 Circuit and functions of each internal block.................................................9
2.1    Central 8 × 8 symmetric TDM switch module....9
2.2     The switch pattern generation block........11
2.3     CODEC module...............................14
2.4     The pattern driver and pattern monitor module..17
2.5     The multiplexer and de-multiplexer modules.....18
3    Hardware implementation environment.............19
3.1 Verilog-XL simulator and Debussy...................19
3.2 Design compiler................................... 21
3.3 DFT (Design for Testability).......................23
3.4 Physical design and verification with Astro........24
4 Simulation and chip testing results..................25
4.1 Functional simulation result..............25
4.2 Gate-level simulation and post-layout simulation result........................................28
4.3 Reports of other tools....................30
4.4 Chip testing results......................32

CHAPTER 3    An 8 × 8 TDM switch with parallel I/O ports using  high speed interface                        35
1    Overall architecture.............................................35
2    Circuit and functions of each internal block....36
3    Simulation results and chip features............38
4    Modified architecture...........................41
4.1 Overall architecture...............................41
4.2 Circuits and functions of each internal block......42
4.3 Simulation result..................................44
CHAPTER 4    A dual-mode 8×8/64×64 symmetric TDM switch with high speed interface                         45
1    Overall architecture.............................................45
2    Circuit and functions of each internal block....47
3    Simulation results..............................49
3.1     Functional simulation result...................49

CHAPTER 5    Conclusions                                     52

Reference                                                54

Appendix                                                 55
A.1 Interface signals of 8 × 8 TDM switch with serial ports....................................................55

                                

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[7]. C. S. Chang, W.J. Chen and H.J. Huang, “On service guarantees for input buffered crossbar switches: a capacity decomposition approach by Birkhoff and von Neumann”, IEEE IWQoS’99, pp. 79-86, London, U.K., 1999.
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