骨牌式動態電路比一般的靜態電路提供了較小的面積及較快的速度，因此骨牌式電路被廣泛地應用在高效能的數位設計中。另一方面，因為製程及設計趨勢不斷地進步，電路在追求更高的效能及更低的功率消耗的同時，也使得電路的運作速度越來越容易受到製程變動及雜訊效應的影響。製程變動及雜訊效應等造成延遲變動的因素可能使一個製作完成的晶片違反預定的時脈限制，像這種時脈不符合要求的電路，雖然能夠正常運作，但因為不能為市場所接受，通常只能報廢，造成良率的下降。傳統上，設計者往往消極地使用較寬鬆的時脈限制來減輕延遲變動的問題，但這個方法卻會無謂地降低電路的效能。在本篇論文中，我們對骨牌式電路提出一個重新合成的方法，以加入額外的輔助電路來達到容忍延遲變動的效果。我們發現在關鍵性的路徑上的邏輯閘較容易受到延遲變動的影響，而改變整個電路的運作速度。因此，我們主要的觀念就在於利用額外加入的電路，來增加這些在關鍵性的路徑上的邏輯閘對延遲變動的容忍度，使電路的效能不會隨著少量的延遲變動產生波動，進而提高良率。實驗結果顯示，經過我們所提出的方法重新合成過的電路，在蒙地卡羅模擬中超過預定的時脈限制的數量，比原本的電路多出約20%。我們將所有蒙地卡羅樣本的時序描繪成分布曲線，可以發現重新合成後的電路的時序分布較原本的電路集中，表示新電路較不易受到製程變動及雜訊效應等造成延遲變動的因素影響。

Factors of delay variation such as process variation and noise effects may cause a manufactured chip to violate the pre-specified timing constraint. Traditional methods add a pessimistic timing margin to alleviate delay variation problems. In this thesis, we propose a re-synthesis technique to tolerate delay variation for domino circuits. Note that slacks of nodes along critical paths is zero; any delay addition to those zero-slack nodes will worsen the final performance of a circuit. Our basic idea is to increase slacks of nodes in the critical region by appending a redundant auxiliary sub-circuit to the original circuit. The auxiliary sub-circuit can cause critical paths to become false paths or imperceptible paths [8] so as to improve the capability of delay variation tolerance. Experimental results are very encouraging.

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