在這篇論文中，我們探討晶片堆疊的系統封裝設計的佈局規劃問
題，在此設計中金屬線結合的方法被用來連接不同晶片間的訊號。我
們提出一個方法，此方法從下而上對每個晶片依序產生一個佈局規劃
的結果使得此佈局規劃的結果有最小的繞線長度且滿足給定的溫度
以及固定邊框的限制。對每個晶片而言，為了找出如此的佈局規劃結
果，我們修改一個已存在的固定邊框佈局規劃器藉由加入幾個考慮溫
度的方案，此佈局規劃器是以模擬退火法為基底。實驗的數據被提供
來展現我們方法的效率以及效果。就我們所知，我們的作品是第一個
有潛力的佈局規劃方法針對晶片堆疊的系統封裝設計。

In this thesis, we study a floorplanning problem for die-stacking System-in-Package (SiP)
designs in which the wire bonding method is used to connect signals between different
dies. We present an approach which sequentially determines a floorplan for each die from
bottom to top such that the generated
floorplan has minimal on-chip wirelength and
satisfies given temperature and fixed-outline constraints. To find such a floorplan for each
die, we modify an existing simulated annealing based fixed-outline floorplanner by adding
several temperature-aware schemes. The experimental results are provided to show the
efficiency and effectiveness of our approach. To our best knowledge, our work is the first
one to give a promising floorplanning approach to die-stacking SiP designs.

[1] S. Adya and I. Markov. Fixed-outline
floorplanning: enabling hierarchical design.
IEEE Transactions on Very Large Scale Integration Systems, 11(6):1120{1135, Dec
2003.
[2] S. N. Adya and I. L. Markov. Fixed-outline
floorplanning through better local search.
In Proceedings of International Conference on Computer-Aided Design, pages 328{
333, 2001.
[3] S. N. Adya and I. L. Markov. Consistent placement of macro-blocks using
floorplanning and standard-cell placement. In Proceedings of International Symposium
on Physical Design, pages 12{17, 2002.
[4] S. Al-sarawi, D. Abbott, and P. Franzon. A review of 3-d packaging technology. IEEE
Transactions on Components, Packaging, and Manufacturing Technology - Part B,
21(1):2{14, Feb 1998.
[5] K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu. On thermal ef-
fects in deep sub-micron VLSI interconnects. In Proceedings of Design Automation
Conference, pages 885{891, 1999.
[6] Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu. B*-Trees: a new represen-
tation for non-slicing
floorplans. In Proceedings of Design Automation Conference,
pages 458{463, 2000.
[7] T.-C. Chen and Y.-W. Chang. Modern
floorplanning based on fast simulated anneal-
ing. In Proceedings of International Symposium on Physical Design, pages 104{112,
2005.
[8] T.-C. Chen, Y.-W. Chang, and S.-C. Lin. IMF: interconnect-driven multilevel floor-
planning for large-scale building-module designs. In Proceedings of International
Conference on Computer-Aided Design, pages 159{164, 2005.
[9] T.-C. Chen, Y.-W. Chang, and S.-C. Lin. A new multilevel framework for large-scale
interconnect-driven
floorplanning. IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, 27(2):286{294, Feb 2008.
[10] T.-Y. Chiang, S. Souri, C. O. Chui, and K. Saraswat. Thermal analysis of heteroge-
neous 3D ICs with various integration scenarios. In Technical Digest of International
Electron Devices Meeting, volume 31, pages 1{4, 2001.
[11] W. K. Chu and W. H. Kao. A three-dimensional transient electrothermal simulation
system for IC's. In Proceedings of International Workshop on Thermal Investigation
of ICs and Systems, pages 201{207, Sep 1995.
[12] J. Cong, J. Wei, and Y. Zhang. A thermal-driven
floorplanning algorithm for 3D
ICs. In Proceedings of International Conference on Computer-Aided Design, pages
306{313, 2004.
[13] L. Golick, J.Goodelle, and T. Shilling. SiP modules call for right blend of tech. In
EE Times, May 2004.
[14] X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C. K. Cheng, and J. Gu. Corner
block list: an eective and ecient topological representation of non-slicing
floorplan.
In Proceedings of International Conference on Computer-Aided Design, pages 8{12,
2000.
[15] S. Im and K. Banerjee. Full chip thermal analysis of planar (2-D) and vertically
integrated (3-D) high performance ICs. In Technical Digest of International Electron
Devices Meeting, pages 727{730, 2000.
[16] G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel hypergraph parti-
tioning: Applications in VLSI domain. In Proceedings of Design Automation Con-
ference, pages 526{529, 1997.
[17] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by simulated annealing.
In Science, May 1983.
[18] J.-M. Lin and Y.-W. Chang. TCG: a transitive closure graph-based representation
for non-slicing
floorplans. In Proceedings of Design Automation Conference, pages
764{769, 2001.
[19] Y.-C. Lin. Pad assignment for die-stacking system-in-package design. In Master
Thesis, Department of Computer Science, National Tsing Hua University, 2009.
[20] H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. Rectangle-packing-based
module placement. In Proceedings of International Conference on Computer-Aided
Design, pages 472{479, 1995.
[21] K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan.
Temperature-aware microarchitecture. In Proceedings of International Symposium on
Computer Architecture, pages 2{13, Jun 2003.
[22] C.-H. Tsai and S.-M. Kang. Cell-level placement for improving substrate thermal
distribution. IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, 19(2):253{266, Feb 2000.
[23] Y. Tsui, S. Lee, J. Wu, J. Kim, and M. Yuen. Three-dimensional packaging for
multi-chip module with through-the-silicon via hole. In Proceedings of Electronics
Packaging Technology Conference, pages 1{7, Dec 2003.
[24] P. Wilkerson, A. Raman, and M. Turowski. Fast, automated thermal simulation of
three-dimensional integrated circuits. In Proceedings of Intersociety Conference on
Thermal and Thermomechanical Phenomena in Electronic Systems, volume 1, pages
706{713, June 2004.
[25] R. Wilson. SiPs form good soc alternative, but designer beware. In EE Times, May
2006.
[26] E. Wong and S. K. Lim. 3D
floorplanning with thermal vias. In Proceedings of
Conference on Design, Automation and Test in Europe, pages 878{883, 2006.