500MHz 低抖動金氧半頻率合成器使用自偏壓寬頻寬鎖相迴路架構

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研究生：	林勝斌 Sheng-Bin Lin
論文名稱：	500MHz 低抖動金氧半頻率合成器使用自偏壓寬頻寬鎖相迴路架構 A 500MHz Low-Jitter CMOS Frequency Synthesizer Using a Self-Biased Wideband PLL Architecture
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	80
中文關鍵詞：	低抖動、頻率合成器、鎖相迴路
外文關鍵詞：	Low-Jitter, Frequency Synthesizer, PLL, Phase Lock Loop
相關次數：	點閱：4 下載：0
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本論文提出一個低抖動鎖相迴路的設計，此ㄧ低抖動鎖相迴路是以自偏壓、與寬頻寬兩種技術為基礎，來達到低抖動設計最後目的。
使用自偏壓技術，可以避免外接偏壓電源，而一般外接偏壓電源電路為 ”Bandgap Reference”，而 Bandgap 產生器又大又複雜，而且以外接的方式會對整個鎖相迴路產生額外的雜訊，進而造成大的抖動。自偏壓的電路在整個鎖相迴路的迴路中，自偏壓可以產生內部迴路所需的電流、電壓，而且自偏壓技術提供固定的頻寬與操作頻率的固定比值，此比值與製程、溫度、電壓無關，以上種種的特性顯示自偏壓可以降低抖動。
要再進一步達成低抖動，我們使用寬頻寬技術，一般鎖相迴路雜訊來源主要有兩個：一個是來自輸入、另一個來自壓控振盪器，而輸入方面我們假設輸入為晶體振盪器，晶體振盪器的雜訊很小，所以我們假設鎖相迴路雜訊來源主要來自壓控振盪器，根據雜訊由壓控振盪器到鎖相迴路輸出的數學轉換方程式知：頻寬要越大越好，寬頻寬有助於降低抖動。
此電路的模擬是採用0.35um 金氧半製程，電源電壓為3.3伏，模擬軟體為HSPICE，由模擬的結果顯示：以自偏壓與寬頻寬技術為基礎的頻率合成器，可以產生峰值對峰值抖動53.9ps 與均方根抖動9.216ps，以上抖動值的模擬結果為頻率合成器操作頻率為450MHz 、且不加電源電壓雜訊。

A design of the low jitter phase-locked loop based upon self-biased and wideband techniques are presented. Avoiding the need of external biasing, self-biasing generates all the internal bias currents and voltages and has fixed bandwidth to operate frequency ratio independent of process, voltage and temperature. This property minimizes jitter, and to further reduce the jitter, the loop bandwidth should be set as wide as possible. Simulated in 0.35um CMOS with supply of 3.3V, the synthesizer can achieve peak to peak jitter 53.9ps and RMS jitter 9.216ps at 450MHz operating frequency.

CONTENTS
Abstract …………………………..……..……………………….1
Contents…….................................................................2
List of figures.    4
List of tables.........    6
Chapter1  Introduction.....................................................................................7
   1.1 History................................................................................................................. 7
   1.2 Motivation........................................................................................................... 7
   1.3 Design Issue and Solutions............................................................................. 8
   1.4 Organization of Thesis..................................................................................... 9

Chapter2  PLL Loop components and Noise.................................... 11
2.1 Phase-Frequency Detector and Charge-Pump..........................................11   2.2LoopFilter........................................................................................................ 16
2.2.1FirstOrderLoop.................................................................................. 17
      2.2.2 Second-Order Type-Two Loop....................................................... 19
       2.2.3 Third-Order Type-Two Loop.......................................................... 21
   2.3 Voltage-Controlled Oscillator.................................................................... 23
      2.3.1 Ring Oscillator VCOs........................................................................ 24
             2.3.1.1 Single-Ended Ring Oscillator........................................... 25
           2.3.1.2 Differential Ring Oscillator............................................... 25
      2.3.2 LC VCOs............................................................................................... 26
   2.4 Dividers............................................................................................................ 27
       2.4.1 Integer-N Divider................................................................................ 27
       2.4.2 Fractional-N Divider........................................................................... 27
   2.5 Noise................................................................................................................... 28
       2.5.1 Jitter....................................................................................................... 28
2.5.1.1 Cycle-to-Cycle Jitter......................................................... 29
            2.5.1.2 Long-Term Jitter................................................................. 29
              2.5.1.3 Root Mean Square Jitter................................................... 30
            2.5.1.4 Peak to Peak Jitter...............................................................32
       2.5.2 Phase Noise..........................................................................................33
Chapter3  Proposed PLL Architecture and Simulation Results................................................................................................36
      3.1 Architecture.............................................................................................. 36
      3.2 Phase-Frequency Detector.................................................................... 37
      3.3 Symmetric Load...................................................................................... 39
      3.4 Zero-Offset Charge Pump..................................................................... 40
3.5 Loop Filter................................................................................................ 43
   3.5.1 First-Order Loop Filter................................................................ 44
    3.5.2 Second-Order Loop Filter.......................................................... 46
 3.6 Differential Buffer Stage..................................................................... 49
 3.7 Bias Generator....................................................................................... 50
 3.8 VCO......................................................................................................... 52
 3.9 Divider..................................................................................................... 54
 3.10 Other Parameters Measurement and Calculation....................... 56
 3.11 Jitter Measurement and Comparison of Recent Work.............. 58
Chapter4  Monte-Carlo Analysis............................................................. 65
        4.1 Performing Monte-Carlo Analysis................................................... 65
        4.2 Monte-Carlo Analysis Results.......................................................... 66
Chapter5  PLL Application......................................................................... 73
         5.1 Clock Skew Suppression.................................................................. 73
         5.2 Clock Recovery................................................................................... 74
         5.3 Frequency Synthesis........................................................................... 74
  5.4 Modulators and Demodulators........................................................ 75
  5.5 Jitter and Phase Noise Reduction................................................... 76
  5.6 Noise Suppression...............................................................................77
Chapter6 Conclusions.........................................................................................78
Bibliography..................................................................................................79
List of Figures

Fig. 1.1 Noise in wideband PLLs………………………………..……………………….9
Fig. 1.2 Noise in narrow and wide bandwidth................................................................9
Fig. 2.1 (a)SR flip-flop phase-detector (b) SR flip-flop PD operation.    11
Fig. 2.2 (a)Phase/Frequency detector (b) PFD operation.    13
Fig. 2.3 PFD response to non-equal input frequencies.    14
Fig. 2.4 PFD dead-zone    14
Fig. 2.5 PFD with charge pump    15
Fig. 2.6 Root-locus plot of a first-order PLL.    18
Fig. 2.7 Open-loop Bode-plot of a first-order PLL.    18
Fig. 2.8 Root-locus plot of a second-order type-two PLL.    20
Fig. 2.9 Open-loop Bode- plot of a second-order type-two PLL.    20
Fig. 2.10 Root-locus plot of a third-order type-two PLL..    22
Fig. 2.11 Open-loop Bode- plot of a third-order type-two PLL    22
Fig. 2.12 (a) Single-ended ring oscillator buffer stage, (b) implementation of one stage. …………………………………………………………………………………25
Fig. 2.13 (a) Differential ring oscillator with odd number of stages, (b)differential ring oscillator with even number of stages…………………………………..26
Fig. 2.14 Differential ring oscillator buffer stage……………………………………26
Fig. 2.15 Illustration of clock jitter    …..28
Fig. 2.16 Illustration of cycle-to-cycle jitter…….……………………………………29
Fig. 2.17 Illustration of long-term jitter………………………………………………….29
Fig. 2.18(a) Periodic signal (b) Random signal………………………………………….30
Fig. 2.19 Average noise power calculation………………………………….……..…31
Fig. 2.20 Random signal and its distribution…………………………………………32
Fig. 2.21 PDF of a Gaussian distribution with a variance of 1……………….………….33
Fig. 2.22(a) Spectrum of an ideal carrier. (b) Noise skirts around the carrier…………34
Fig. 2.23 Phase noise (ratio of the dark grey area to the light grey area)………………34
Fig. 2.24 The effect of phase noise in a receiver………………………….……………35
Fig. 3.1 Self-biased PLL block diagram……………………………..…….…………….37
Fig. 3.2 PFD with equal short duration output pulses for in-phase inputs........................38
Fig. 3.3 Simulation results of PFD when Fdb as same as Ref…………………………...38
Fig. 3.4 Simulation results of PFD response to non-equal input frequencie………….39
Fig. 3.5 Symmetric load schematic    40
Fig. 3.6 I–V characteristics of the symmetric load and resistor load……………………40
Fig. 3.7 Simulation result of symmetric load.    40
Fig. 3.8 Simplified schematic of charge pump..    42
Fig. 3.9 Complete schematic of charge pump with symmetric loads..    42
Fig. 3.10 Charging with 10pf.    42
Fig. 3.10 Disharging with 10pf.    42
Fig. 3.12 PLL-based frequency synthesizer linear model.……………….…………….43
Fig.3.13 First-order loop filter with input and output signals.........................45
Fig. 3.14 Granular transient response of a PLL with first-order loop filter.......................45
Fig. 3.15 Simulation of first-order loop filter output signal Vctrl.………………….….46
Fig. 3.16 Simulation of first-order loop filter Granular effect……...................................46
Fig. 3.17 Second-order loop filter schematic.…………………………………………....46
Fig. 3.18 Open-loop Bode- plot of 3 pole 1 zero CP-PLL………………………………49
Fig. 3.19 Simulation result of Open-loop Bode- plot using ADI Sim PLL.……………49
Fig. 3.20 Differential buffer delay stage with symmetric loads.    50
Fig. 3.21 Replica-feedback current source bias circuit………………………………..51
Fig. 3.22 imulation result of bias generator...    51
Fig. 3.23 5-stage differential ring oscillator………………………………...……...…....52
Fig. 3.24 VCO output frequency vs. control voltage……….……………………………53
Fig. 3.25 Asynchronous frequency divider with a division ratio of 4…….……………54
Fig. 3.26 D-flip-flop.    54
Fig. 3.27 Simulation result of frequency divider……………………….………………..55
Fig. 3.28 Simulation result of 500 MHz input signal.    55
Fig. 3.29 A 500MHz PLL simulation time.……………………………………………..56
Fig. 3.30 Illustration of phase error...    57
Fig. 3.311000 samples jitter response.…...……………………………………………....59
Fig. 3.321000 samples jitter histogram.……….…………………………………………60
Fig. 3.33 jitter response with 50mV of 1MHz square wave supply noise..……………62
Fig. 3.34 jitter histogram with 50mV of 1MHz square wave supply noise.    62
Fig. 3.35 jitter response with 100mV of 1MHz square wave supply noise……………..63
Fig. 3.36 jitter histogram with 50mV of 1MHz square wave supply noise.……………..63
Fig. 4.1 Monte Carlo Distribution.…...………….……………………………………....66
Fig. 4.210 samples jitter with 5% channel length variation in PLL VCO………….……68
Fig. 4.3100 samples jitter with 5% channel length variation in PLL VCO…..…………68
Fig. 4.4 1000 samples jitter with 5% channel length variation in PLL VCO……………69
Fig. 4.510 samples jitter with 10% channel length variation in PLL VCO……………..71
Fig. 4.6100 samples jitter with 10% channel length variation in PLL VCO…………....71
Fig. 4.7 1000 samples jitter with 10% channel length variation in PLL VCO………..…72
Fig. 5.1 Clock skew in a digital system…..……………………………………..……73
Fig. 5.2 Skew reduction using a PLL……………………………………………….…74
Fig. 5.3 Clock recovery from a transmitted data……………………….…………..74
Fig. 5.4 Frequency Synthesis using a PLL……….……………………………..……75
Fig. 5.5 Angle modulation (PM and FM) using a PLL…………..……………….…75
Fig. 5.6 PLL jitter or phase noise sources……………………..……….…………..76
Fig. 5.7 Transfer function of jitter from input and VCO to the output………….…76
Fig. 5.8 PLL as a narrowband noise filter…………………..……….……………...77


List of Tables

Table 3.1 Relationship between γ and PM.……….………...……………………..……48
Table 3.2 Loop parameters.……….………………………...……………………..……58
Table 3.3 PLL performance summary.…………...………...……………………..……58
Table 3.4 Jitter results of 10、100、1000 sample periods.………………………..……59
Table 3.5 Jitter results with 50mV of 1MHz square wave supply noise...………..……61
Table 3.6 Jitter results with 100V of 1MHz square wave supply noise…………..……61
Table 3.7 jitter at different operation frequency..………………………..…………...…64
Table 3.8 Comparison of recent work.……………………..…………...…………….64
Table 4.15% Channel Length Variation Using Gaussian Distribution In PLL VCO……67
Table 4.2 10% Channel Length Variation Using Gaussian Distribution In PLL VCO….70

                                

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