研究生: |
黃毓閎 Huang, Yu-Hung |
---|---|
論文名稱: |
一個可應用於硬體輔助型軟硬體協同模擬的非侵入式時間同步介面 A Non-Intrusive Timing Synchronization Interface for Hardware-Assisted HW/SW Co-Simulation |
指導教授: |
蔡仁松
Tsay, Ren-Song |
口試委員: |
許有進
Hsu, Yu-Chin 許雅三 Hsu, Yar-Sun |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊工程學系 Computer Science |
論文出版年: | 2012 |
畢業學年度: | 100 |
語文別: | 英文 |
論文頁數: | 47 |
中文關鍵詞: | 時間同步介面 、硬體輔助型軟硬體協同模擬 |
外文關鍵詞: | Timing synchronization interface, Hardware-assisted HW/SW co-simulation |
相關次數: | 點閱:1 下載:0 |
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本篇論文提出了一個非侵入式時間同步介面,能使硬體輔助型軟硬體協同模擬基於共享資料型同步的方法達到快速且精準的模擬結果。我們的非侵入式時間同步介面裝置是特別針對元件在不透明環境下模擬所設計的。有了這樣的裝置,我們可以系統化的在匯流排上監測共享資料的存取以及控制硬體輔助型元件的推進時間來達到快速且精準的系統軟硬體協同模擬。實驗結果顯示,我們的方法比起基於傳統時脈型同步的硬體輔助型軟硬體協同模擬方法有了十倍到一百四十倍的加速且維持一樣正確的模擬結果。
This paper proposes using a non-intrusive timing synchronization interface approach to facilitate shared-data synchronization for fast and accurate hardware-assisted HW/SW co-simulation. Our synchronization interface device is specially designed for non-transparent components. With the device, we can systematically monitor shared-data accesses on a bus and control the progressing time of hardware-assisted components for fast and accurate system co-simulation. Experiments show that our approach is 10 to 140 times faster than the cycle-based hardware-assisted co-simulation approach.
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