| 研究生: |
邱子宸 Chiou, Tz-Chen |
|---|---|
| 論文名稱: |
應用於大型積體電路之單層二硫化鉬奈米片電晶體製備與電性量測 Fabrication and characterization of monolayer MoS2 nanosheet transistor for VLSI applications |
| 指導教授: |
吳孟奇
Wu, Meng-Chyi |
| 口試委員: |
楊智超
Yang, Chih-Chao 程育人 Cheng, Yuh-Jen |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
| 論文出版年: | 2018 |
| 畢業學年度: | 106 |
| 語文別: | 英文 |
| 論文頁數: | 74 |
| 中文關鍵詞: | 單層 、二硫化鉬 、接觸電阻 、載子遷移率 、短通道 |
| 外文關鍵詞: | Monolayer, MoS2, Contact resistance, Mobility, Short channel |
| 相關次數: | 點閱:196 下載:0 |
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當傳統矽基材料電晶體微縮達到物理極限,為因應未來5奈米以下通道電晶體,尋找替代材料來替代矽基電晶體變得極為重要。對於這樣的微縮電晶體,短通道效應將會嚴重影元件性能和操作。為了降低短通道的影響,在極小尺度下,二維材料比矽有更多優勢。自從石墨稀被成功分離製備後,為二維材料的研究注入許多動能,其中,過渡性金屬硫屬化合物因為獨特的光與電特性受到許多關注,當中以二硫化鉬(MoS2)因為應用範圍廣大和相對較高的電子等效質量,被認為具有很大潛能,能夠替代傳統半導體。
本研究受到清大材料所李奕賢教授實驗室幫助下,成功以使用化學氣相沉積方式製備的高品質和大面積單層二硫化鉬,製作出具高效能單層二硫化鉬電晶體。該電晶體為一平面背閘極結構,採用通道先製的方式製作,通道長寬為奈米等級。閘極氧化層為10奈米二氧化鉿,以原子層化學氣相沉積系統沉積。再者,使用電子束微影系統製作黏附層,以增強接觸電極金的附著力。其後轉移材料,使用電子束微影系統製作第二道光罩,以乾式蝕刻定義通道寬度和完成元件隔離。隨後第三道光罩定義通道長度,使用掀離製程完成接觸電極。接觸電極採用金因為其在環境有良好的穩定性。
本篇研究中,所有電性量測皆在大氣中進行。所製備出來的電晶體具有高輸出電流,最高可達到111(μA/μm)和高載子遷移率81(cm2/Vs),與文獻中以剝離方式或是化學氣相沉積製備的單層二硫化鉬電晶體相比,皆是可以匹敵的。許多提升元件特性方法也在本文中討論,諸如熱退火製程,High k材料應用,另外,載子速度飽和現象,通道調變效應也有在本文中闡明。再者,藉由TLM圖案展示萃取接觸阻抗的方法,經由減去接觸阻抗的影響後,觀察到載子遷移率大幅上升,揭露元件的真實電性。本篇論文旨在製備與改善單層二硫化鉬電晶體特性,為未來相關實驗提供有效的分析工具及方法。
As conventional silicon based transistors approach its scaling limit, searching for the alternative channel material is urgently needed for future sub 5 nanometer gate length devices. For such ultimately scaled transistors, short channel effects become dominant and severely impede electronic device operation. In this regard, to suppress short channel effects, two dimensional (2D) material shows strong potential compared to silicon. Since graphene were prepared successfully in 2004, this breakthrough have inspired many researches on 2D materials. Among various 2D materials, transition metal dichalcogenides (TMDs) have attracted much attention due to its unique optical and electrical properties. Molybdenum disulfide (MoS2), a member of TMDs family, is versatile and have large effective mass, considered to be one of promising candidates for future electronic devices.
In this thesis, high-performance monolayer MoS2 nanosheet transistors have been successfully fabricated. The monolayer MoS2 is grown by chemical vapor deposition, transferred and provided by NTHU Prof. Yi-Hsien Lee’s group. The monolayer MoS2 transistors are in back-gate geometry following channel first fabrication. The devices channel lengths are ranging from 100 nm to 400nm, while channel widths vary from 50nm to 400nm. The gate dielectric is High k HfO2 with thickness 10nm approximately, deposited by atomic layer deposition at 250 degrees. Adhesion layer is defined by electron beam lithography to enhance the metal contact (Au) adhesion. Afterwards, two further electron beam lithography masks were performed for channel width and channel length formation. Channel width is accomplished by dry etching, achieving device formation. Channel length is completed by lift-off process after metal contact (Au) deposited by electron beam evaporation, realizing S/D region. Au is chosen for its stability in ambient.
In this thesis, all electrical measurements were carried out in ambient conditions. The fabricated transistor perform high ON current of 111 μA/μm and intrinsic field effect mobility of 81cm2/Vs without noticeable short channel effect. Without contact optimization, our device are comparable or superior compared with other MoS2 transistors in literature, indicating the high quality of monolayer MoS2 and validity of the fabrication process. Considerable strategies for improving device performance, such as annealing, high k boosting are discussed. In addition, velocity saturation and transistor scaling behavior are also observed and discussed in this work. Moreover, the extraction of contact resistance by TLM pattern are also demonstrated. After subtracting the effect from contact resistance, significant enhancement on mobility are confirmed, uncovering the real device performance.
This work provide a practical route to improve the performance of monolayer MoS2 transistor and useful electrical characterization method.
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