在本篇論文中，我們對於高效能資料路徑設計提出了一個特殊元件辨識的方法，我們所提的方法分為兩個階段：第一個階段是以最佳延遲時間為考量的邏輯合成方式，第二個階段是在佈局中辦識特殊元件。
在第一個方面，我們利用了合成工具將一個RTL的設計轉換成一個達到最快延遲時間的gate階層設計，接著應用以MISA為基礎的方式去分配slack，並且重新作合成去降低面積的成本。

在第二個步驟中，我們提出了branch-and-bound以及heuristic兩個演算法去辨識出為了滿足時間限制需要做成特殊元件的module和cell，並且在實驗結果中證明我們所提出的方法為有效之方法。

In this thesis, we present a custom-cell identification method for high-performance datapath designs. Our proposed method consists of two phases: (1) the maximum-timing-driven RTL/logic synthesis and (2) the custom-cell identification. In the first phase, we use a commercial synthesis tool to convert an RTL design into a gate-level design with an achievable fastest timing, and then apply the MISA-based slack assignment and re-synthesis process to minimize the area cost. In the second phase, we present a branch-and-bound algorithm and a heuristic to identify the module/cell set that needs to be customized in order to satisfy the given timing constraint. Experimental results have been presented to demonstrate the effectiveness of our proposed method.

[1] Chunhong Chen, Xiaojian Yang and Majid Sarrafzadeh, “Potential Slack: An Effective Metric of Combinational Circuit Performance,” Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on, 2000 Page(s): 198 -201
[2] R. Nair, C. L. Berman, P. S. Hauge, and E. J. Yoffa, “Generation of Performance Constraints for Layout,” IEEE Transactions on Computer-Aided Design, CAD-8(8): 860-874, August 1989.
[3] Sarrafzadeh, M.; Knol, D.A.; Tellez, G.E., “A Delay Budgeting Algorithm Ensuring Maximum Flexibility in Placement,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume: 16 11, Nov. 1997, Page(s): 1332 –1341
[4] Jinan Lou; Wei Chen; Pedram, M., “Concurrent logic restructuring and placement for timing closure,” Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on, 1999 Page(s): 31 -35
[5] Chowdhary, A.; Kale, S.; Saripella, P.; Sehgal, N.; Gupta, R., “A general approach for regularity extraction in datapath circuits,” Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on, 1998 Page(s): 332 –339
[6] Kutzschebauch, T.; Stok, L., “Regularity driven logic synthesis,” Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on, 2000 Page(s): 439 –446
[7] Ienne, P.; Griessing, A., “Practical experiences with standard-cell based datapath design tools. Do we really need regular layouts?” Design Automation Conference, 1998. Proceedings, 1998 Page(s): 396 -401
[8] Grundmann, W.J.; Dobberpuhl, D.; Allmon, R.L.; Rethman, N.L., “Designing High Performance CMOS Microprocessors Using Full Custom Techniques,” Design Automation Conference, 1997. Proceedings of the 34th , Page(s): 722 –727
[9] Daily, W.J.; Chang, A., “The Role of Custom Design in ASIC Chips,” Design Automation Conference, 2000. Proceedings 2000, 2000, Page(s): 643 -647
[10] Panda, R.; Dharchoudhury, A.; Edwards, T.; Norton, J.; Blaauw, D., “Migration : A new technique to improve synthesized designs through incremental customization,” Design Automation Conference, 1998. Proceedings , 1998 Page(s): 388 –391
[11] Fishburn et. al., “Tilos: A posynomial programming approach to transistor sizing,” ICCAD, pp326-328, 1985.
[12] Neman, M.; Tiwari, V., “Macro-driven circuit design methodology for high-performance datapaths,” Design Automation Conference, 2000. Proceedings 2000 , 2000 Page(s): 661 –666
[13] TSMC 0.35 micron 1P4M CMOS.
[14] Synopsys Design Compiler Reference Manual v1999.10-5”, Synopsys, 1999.
[15] Synopsys Design Time Reference Manual.
[16] IC Layout Command Reference Manual, Release 1999.4.