在現今積體電路設計中，三維整合技術在半導體行業中具有顯著的潛
力，而在面對面三維積體電路設計中不同的晶片可以使用不同的元件庫，
一些現有的三維物理設計流程使用二維商業工具來處理三維積體電路物理
設計。這些當前的流程初步將三維設計轉化為二維，然後在流程的最後階
段將其恢復為三維積體電路設計。有幾項研究指出，在這從二維到三維的
恢復過程中，設計品質會有所降低。而其他的三維全局放置器可以在三維
空間中優化設計，並在全局放置階段之後決定一個元件屬於哪個晶片，然
而，這沒有考慮到在不同晶片上有不同元件庫所造成的差異。在我們的論
文中，我們採用靜電類比方法來建立三維積體電路設計中的密度函數模型，
提出了一種優化巨集之旋轉方向的方法，並為混合尺寸設計引入了更為精
確的評估收斂方法。實驗結果證明，我們的方法是有效的，可以直接優化
使用不同元件庫的晶片組成的三維設計。

In current IC design, 3D integration technology has significant potential in the semiconductor industry. Face-to-Face 3D-ICs can be implemented using different cell libraries. Some existing 3D physical design flows utilize 2D commercial tools to handle the physical design of 3D integrated circuits. These current flows initially convert the 3D design into 2D and then restore it to a 3D design in the final stages of the flow. However, several studies indicate a degradation of design quality during this restoration process from 2D to 3D. The other 3D global placers can optimize the design in a three-dimensional space and decide which die a cell belongs to after the global placement stage. However, it does not consider the difference caused by distinct dies utilizing different cell libraries. In this thesis, we use the electrostatic analogy approach to model a density function in 3D-IC design, propose a method for optimizing the rotation orientation of macros, and introduce a more precise evaluation convergence method for mixed-size design. Experimental results demonstrate that our approach is effective and can directly optimize 3D designs using different cell libraries for each die.

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