在超大積體電路後段製程中，晶圓廠除了提供設計電路的廠商設計規則 (Design rule) 外，也會提供很多連線的主流測試結構的電容以及電阻值，而這些電容電阻值將會影響整個電路的設計，也關係著良率的問題，所以其準確度就顯得相當重要，因此準確的模擬其連線的電容等電性，才能提高良率。在乾蝕刻 (Dry etch) 製程過程中，因為蝕刻速率的不同有了微負載效應，以前為了解決此效應使用了高介電常數 (High-K) 的介電層，被稱為蝕刻禁止層。但因為製程技術的演進，晶片的效率的需求變高，RC 延遲也就愈來愈重要。為了減少RC延遲，製程也朝著減少高介電常數的介電層的使用，一但減少了這些介電層，金屬線的大小就會受微負載效應的影響。本論文探討微負載效應對電容的影響，模擬了微負載效應下的金屬線大小，進而模擬出在微負載效應下的電容值，再與無微負載效應下的電容值來做比較，了解其電容差異。然而在很多情況下此差異大於10%，有時更在30%到50%之間。本論文讓我們了解到，在現今製程中，要準確的模擬連線的電容，則需要考慮到微負載效應。

The foundry provides not only the design rules but also resistances and capacitances of the mainstream test structures of interconnect for designers in the process of the back-end of line of VLSI. These capacitances and resistances affect the design of circuits and yield, so the accuracy of RC extraction is very important. Accurately simulating the capacitances and resistances of interconnect will add the yield of chips. During the process of the dry etch, there will be the microloading effect because of different etch rate. In early age, the dielectric layers with high dielectric constant (High-K) are used to avoid the effect, which are known as etch stop layers. Because the technology of process grows up and the requirement of the performance of the chips increases, RC delay is more important. In order to reduce RC delay, decreasing the use of the dielectric layers with high constant becomes a trend in the modern process. Thus, the dimensions of metal lines will be affected by microloading effect. This paper focuses on the impact of microloading effect to the capacitance of interconnect. And there is simulation on how the dimensions of metal lines change under microloading effect and capacitance extraction based on the dimension simulation just mentioned. Beside, it compares these capacitances with the capacitance without microloading effect to understand the difference between them. It becomes greater than 10% in many cases. There are several important cases where around 30% to 50% are observed. In brief, the paper lets us to know that it is necessary to consider the microloading effect, if we want to simulate the capacitances of interconnect more accurately in the modern process.

[1]. Keh-Jeng Chang, Soo-Young Oh, and Ken Lee, “HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs”, 1991 Nov. 11-14.
[2]. Tarik Bourouina, Takahisa Masuzawa, and Hiroyuki Fujita, “The MEMSNAS Process: Microloading Effect for Micromachining 3-D Structures of Nearly All Shapes”, 2004 April.
[3]. Junghoon Yeom, Yan Wu, Mark A. Shannon, “Critical Aspect Ratio Dependence in Deep Reactive Ion Etching of Silicon”, 2003 June 8-12.
[4]. M. Tada, Y. Harada, K. Hijioka, H. Ohtake, T. Takeuchi, S. Saito, T. Onodera, M. Hiroi, N. Furutake and Y. Hayashi, “Cu Dual Damascene Interconnects in Porous Organosilica film with Organic Hard-mask and Etch-stop layers For 70nm-node ULSIs”, 2002.
[5]. James D. Plummer, Michael D. Deal, Peter B. Griffin, “SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling”.
[6]. 奈米通訊。第六卷第三期36.雙鑲嵌結構製作技術簡介。http://www.ndl.gov.tw/ndlcomm/P6_3/36.htm
[7]. 胡恩崧，淺溝絕緣層平坦化之製程因數改善，私立中原大學機械工程學系研究所，2003.6。
[8]. 劉柏村、張鼎張，低介電常數材料應用於導體連線製程技術的探討，國家奈米元件實驗室。
[9]. 張秋貴，應用實驗設計法調整蝕刻製程程式以改善晶圓允收測試之接觸窗阻值電性之研究，2003 .1。
[10]. SYNOPSYS, Raphael Reference Manual, Version 2003.09, September 2003.
[11]. Excerpt from: Silicon Processing for The VLSI ERA - Vol. 4, p. 674-679 15.4 Introduction to Dual-Damascene Interconnect Processes by Stanley Wolf, Ph.D. , http://www.latticepress.com/damascene.html