研究生: |
陳珮琳 Chen, Pei-Lin |
---|---|
論文名稱: |
嵌入式電流模式非揮發性類比記憶體研發 The development of embedded, current-mode non-volatile analog memory |
指導教授: |
陳新
Chen, Hsin |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2010 |
畢業學年度: | 98 |
語文別: | 中文 |
論文頁數: | 104 |
中文關鍵詞: | 非揮發性 、類比記憶體 |
外文關鍵詞: | nonvolatile, analog memory |
相關次數: | 點閱:4 下載:0 |
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仿神經系統之中,儲存類比値參數於懸浮閘內,可以使系統不經數位類比轉換,執行大量之平行運算;但文獻中的記憶體元件大部分是使用EEPROM技術,而非嵌入式記憶體元件。雖然有文獻有提出相容於標準製程(嵌入式)之實現方式,但準確度卻會受到非線性寫入機制和元件製程誤差的限制,為了提高解析度,有些文獻使用晶片外部之寫入系統或者外接高解析度比較器,但如此便會提高系統之複雜性。
本研究的主要目標希望在標準0.35微米互補型金氧半製程下設計嵌入式非揮發性類比記憶體,其設計原則著重於非揮發性、操作簡單、快速寫入(寫入時間於<1ms)以及具有高精準度(八位元解析度)等四項特性。本論文中,依據先前我們研究量測的結果,進一步改善寫入速度、破壞性讀取以及精準度等這些特性。經改良後下線量測並與模擬相比較,以及驗證量測結果是否符合原理的推論。除了電路設計上的改變,本論文為了提供類比記憶體電路模擬時的熱載子注入模型,將不同尺寸P-型電晶體萃取出的熱載子效應趨近模型之製程參數(α、β)加以歸納整理,並得出一定規律性之後,便藉此規律性預估不同元件尺寸之熱載子效應趨近模型。最後設計出在標準0.35微米互補型金氧半製程下,非破壞性讀取且有八位元解析度的類比記憶體單元後,提出陣列式類比記憶體電路架構。
[1]M. Holler, S. Tam, H. Castro, and R. Benson, "An Electrically Trainable Artifical Nerual Network with 10240 ‘Floating Gate’ Synapse," Proc. Of the int. Joint Conf. on Neurak Networks, Vol. II, 1989, pp. 191-196.
[2]H.V. Tran, et al., "A 2.5V 156-level Non-volatile Analog Storage Device Using EEPORM Technology," Proceeding of IEEE Internalf Solid-State Circuits Conf., 1996, pp. 270-171.
[3]C. Diorio, et al., "Adaptive CMOS: from biological inspiration to systems-on-a-chip," Proceedings of the IEEE, vol. 90, pp. 345-357, 2002.
[4]G. Serrano, et al., "Automatic Rapid Programming of Large Arrays of Floating-gate Elements," IEEE Int. Symp. On Circuits and Syst., vol. 1, no., pp. I-373-I-376 Vol.1, 23-26, May 2004.
[5]S. Atsumi, et al., "Fast programmable 256K read only memory with on-chip test circuits," IEEE Journal of Solid-State Circuits, vol. 20, pp. 422-427, 1985.
[6]H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O’Connell, and R. E. Oleksiak, “The variable threshold transistor, a new electrically alterable non-destructive read-only storage device,” IEEE IEDM Tech. Dig., Washington, D.C., 1967.
[7]X. Wang, J. Liu, W. Bai and D. L. Kwong, “A novel MONOS-type non-volatile memory using high-k dielectrics for improved data retention and programming speed,” IEEE Trans. Electron Devices, vol. 51, pp. 597-602, April 2004.
[8]J. Van Houdt, et al., "The HIMOS flash technology: the alternative solution for low-cost embedded memory," Proceedings of the IEEE, vol. 91, pp. 627-635, 2003.
[9]D. Kim, et al., "Stacked gate mid-channel injection flash EEPROM cell. I. Programming speed and efficiency versus device structure," IEEE Transactions on Electron Devices, vol. 45, pp. 1696-1702, 1998.
[10]S. Ogura, et al., "Low voltage, low current, high speed program step split gate cell with ballistic direct injection for EEPROM/Flash," IEDM Tech. Dig, p. 987¡V990, 1998.
[11]C. Diorio, et al., "A floating-gate MOS learning array with locally computed weightupdates," IEEE Transactions on Electron Devices, vol. 44, pp. 2281-2289, 1997.
[12]K. Kim, et al., "An 8-bit-resolution, 360-μs write time nonvolatile analog memorybased on differentially balanced constant-tunneling-current scheme(DBCS)," IEEE Journal of Solid-State Circuits, vol. 33, pp. 1758-1762, 1998.
[13]K.-H. Kim and K. Lee, “A true nonvolatile analog memory cell using coupling charge balancing,” in ISSCC Dig. Tech. Papers, pp. 268–269, 1996.
[14]C. Diorio, et al., "A high-resolution non-volatile analog memory cell," Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 3, pp. 2233–2236 , 1995.
[15]S. Kinoshita, et al., "New non-volatile analog memory circuits using PWM methods," IEICE TRANSACTIONS ON ELECTRONICS E SERIES C, vol. 82, pp. 1655-1661, 1999.
[16]S. Kinoshita, et al., "A PWM analog memory programming circuit for floating-gate MOSFETswith 75-μs programming time and 11-bit updating resolution," IEEE Journal of Solid-State Circuits, vol. 36, pp. 1286-1290, 2001.
[17]R. Harrison, et al., "A CMOS programmable analog memory-cell array using floating-gate circuits," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, pp. 4-11, 2001.
[18]P. Smith, et al., "Accurate programming of analog floating-gate arrays," in Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 5, (Scottsdale, AZ), pp. V-489-V-492 , May 2002.
[19]S. Tam, P. K. Ko. And C. Hu, “Lucky-Electron Model of Channel Hot-electron injection in MOSFET’s,” IEEE Trans. Electron Devices, Vol.
ED-31, No. 9, pp. 1116-1125, 1984.
[20]K. Hasnat, CF Yeap, S. Jallepalli, WK Shih, SA Hareland, VM Agostinelli, AF Tasch,and CM Maziar, “A Pseudo-Lucky electron model for simulation of electron fate current in submicron N-MOSFET's,” IEEE Tran. Electron devices, vol.43, no.8, pp.1264-1266, August 1996.
[21]K. Lee, et al., "Self-convergent scheme for logic-process-based multilevel/analog memory," IEEE Transactions on Electron Devices, vol. 52, pp. 2676-2681, 2005.
[22]James Brennan, Jr, Sartoga, Calif. “Negative voltage switching circuit”, the U.S. patents 5,701,272, 1997.
[23]闕隆ㄧ,嵌入式快閃式記憶體中新行參考電壓和字線解碼電路的設計,碩士論文,國立清華華大學,2002。