採用多種工作電壓在單晶片系統的設計上是一條實現低功率的有效途徑。但是，假如我們將每個核心都設定在相對應的最低工作電壓，這樣可能會導致複雜的電壓網路以及大量的電位移轉器。針對設定工作電壓的問題，我們提出了兩種規劃方法。一是比較精確但是需要較長的計算時間。二是可以提供非常快速的解決方法而且產生出來的解答近乎最佳。此外，我們還修改了傳統的平面規劃架構。與以往的研究相比，我們可以最佳化整體功率消耗、電位移轉器負擔、電壓網路複雜度，並且不會犧牲掉線路長度跟面積。在實驗數據中，當我們在產生電壓島時，我們可以減少17-53%,的電力消耗。

Reducing power is an important issue in modern core-based
SOC designs. Using multiple supply voltages on a SoC design is an efficient way to achieve low power. However, it may lead to a complex power network and a huge number of level shifters if we just set the cores to operate at their respective lowest voltage levels. We present two formulations for the voltage level assignment problem. The first is exact but takes longer time to compute a solution. The second can be solved much faster with virtually no loss on optimality. In addition, we propose a modification to the traditional floorplanning framework. Unlike
previous works, we can optimize the total power consumption, the level shifter overhead, and the power network complexity without compromising the wirelength and the chip area. In the experiments, we obtained 17- 53\% power savings with voltage island generation.

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