隨著CMOS 製程與半導體自動化技術快速的演進，系統單晶片設計也變的越來越有實用價值與普及化。將各種不同的單獨IP 整合到單一個晶片中能夠達成較少的面積，較低的功率與叫高速的設計。然而，這些不同性質的IP 之間的相互通訊是利用許多平行匯流排來相互連接。這樣的連接方式可能會造成一些問題，如：繞線的負擔，具有較大的電容負載，較大的功率消耗，較大的面積消耗與傳輸延遲的負擔。
然而，將平行匯流排利用多工的方式整合成一條串列連接會增加功率消耗。因此，為了解決這個問題，我們提出了嵌入式反相編碼架構來減少串列連接介面的功率消耗與避免延遲的問題，不像其他的編碼方式需要在編碼單位去增加額外位元。另外一方面，我們針對不同的多工器數目提出了選擇通訊線之間的最佳距離來達到最小的寄生電容效應與面積消耗。當使用最佳的多工器數目，最佳的寬度與距離，能量消耗能夠達成最小化。藉由使用這些最佳的參數，我們所提出的嵌入式反相編碼架構能夠比平行匯流排的方式節省30% 到70%。
在高效能的單晶片系統中，較高的運作頻率將會減少時間邊界(timing margin)。當時間邊界很嚴格的時候，時序誤差與時序偏差將會導致IC與IC之間同步的難度增加。延遲鎖相迴路是常用來達成同步目的方法之一。因此我們提出了一個以延遲鎖相迴路為基礎的倍頻器，它結合了PMOS主動式負載與可適性主體偏壓電路。PMOS主動式負載是具有inductive-peaking效應來增加電路的運作頻率範圍。可適性主體偏壓電路互斥或電流式邏輯電路比傳統的互斥或電流式邏輯電路功率消耗節省54.9%。所提出的倍頻器能夠產生延遲元件數目的頻，其中當延遲元件的數目是偶數時。所提出的倍頻器的運作範圍為80MHz到2.1GHz,所測量到的峰值對峰值時序偏差在300MHz是0.56ps，在80MHz是70ps.功率消耗在2.1GHz時是30mW, 峰值對峰值時序偏差為26.7ps。
串列傳輸介面也可以用在影音/影像傳輸，當一個影像藉由傳送端傳送之後，被傳輸的影音/影像可能會包含雜訊，如高斯雜訊與白雜訊。因此，如何能夠有效率的移除被接收影音/影像中的雜訊且能夠保持它本身的特性是一件很重要的事。因此，我們提出了一個切換式雙邊濾波器，並且結合紋理與雜訊偵測能去除混合式的雜訊模型。基本上的概念是先偵測然後如果有雜訊便進行濾波，若判斷沒有雜訊便不進行濾波處理。針對偵測方面，我們提出象限中間值排序向量(SQMV)架構的方法，它能提供許多重要的訊息，像是在目前處理的位置中是否存在任何影像邊緣或是細節的資訊。並且可以從這些資訊裡再從SQMV中確定出一個參考中間值來代表目前影像位置的特性。在雜訊偵測器中，參考中間值用來跟目前的像素比較，並且判定目前的像素點是一個脈衝雜訊、高斯雜訊或是一個沒有雜訊的點。切換式雙邊濾波器確實能夠有效去除高斯與脈衝這兩種雜訊模型。依照目前判斷出的雜訊模型，來切換雙邊濾波器中差值濾波器的部份。模擬結果顯示我們設計的雜訊偵測器對於這兩種雜訊模型不僅有很高的雜訊偵測率，也有很高的雜訊分辨率。切換式雙邊濾波器能夠達到很高的峰值信噪比與極佳的影像結果，與其他大部分濾波器不同的是，我們設計的切換式雙邊濾波器，不僅能夠去除單一雜訊模型，也能夠很有效地處理混合性的雜訊模型，其一是胡椒鹽雜訊混合均勻脈衝雜訊，另一個是胡椒鹽雜訊混合高斯雜訊。

As the advance of the CMOS process and electronic design automation (EDA) technology, the SoC design becomes more and more practical and popular. Various individual IPs are integrated together into a single chip to achieve lower area, lower power and higher speed design. However, a lot of parallel lines communicate between heterogeneous IPs. It will be marked as routing overhead, large capacitive load, large power consumption, large area and propagation delay overhead. However, the power consumption will increase when multiplexing parallel bus into a serial link. Therefore, we propose an embedded transition inversion (ETI) coding to reduce the power consumption of serial link without extra bit in the codeword to avoid the latency problem in other coding schemes. In addition, we propose a selective spacing (SS) method to choose the minimum parasitic capacitance and area consumption for different value of multiplexing. This ETI coding scheme reduces the transition by up to 31% compared with the encoding followed by serial (ES) scheme. For analysis and simulation results, this study indicates that the proposed coding scheme produces a low bit transition for different kinds of data patterns. Using the optimum degree of multiplexing, optimum width and spacing, the bus energy dissipation can be minimized. Using these optimum parameters, the ETI coding scheme achieves 30% to 70% less energy compared with the parallel bus. The higher operating frequency will decrease the timing margin for high-performance SoC systems. As the timing margin is tight, the timing skews and jitters would make it difficult to synchronize among IC modules. Delay locked loops (DLL) has been typically employed for purpose of synchronization. A wide-range, low-power delay-locked loop based (DLL-based) frequency multiplier with the PMOS active load and adaptive body biasing (ABB) circuit is proposed. Adding the PMOS active load in the delay cell has the inductive-peaking effect to increase the operation frequency range. With the clocked-power ABB current mode logic (CML) exclusive-OR (XOR) circuit, the frequency multiplier can achieve power saving to 54.9% compared with conventional CML XOR circuits. The frequency multiplier can generate N times of frequency of the input clock when the number of delay cells (N) in the Voltage Control Delay Line (VCDL) is even. The proposed DLL-based frequency multiplier can operate from 80MHz to 2.1GHz using 0.18μm CMOS process. The measured peak-to-peak jitters of the DLL core are 30.56ps at 330MHz
and 70ps at 80MHz. The power consumption and jitter of the proposed frequency multiplier at 2.1GHz are 30mW and 26.7ps, respectively. The SerDes interface can also apply to video transmission. In general, when an image is transmitted by the transmitter, the transmitted video may be included noise such Gaussian noise and White noise. Therefore, an important problem of video/image processing is to effectively remove noise from a received image while
keeping its features. Therefore, we propose a switching bilateral filter (SBF) with a texture and noise detector for universal noise removal. Operation was carried out in two stages: detection followed by filtering. For detection, we propose the sorted quadrant median vector (SQMV) scheme, which includes important features such as edge or texture information. This information is utilized to allocate a reference median from SQMV, which is in turn compared with a current pixel to classify it as impulse noise, Gaussian noise, or noise-free. The SBF removes both Gaussian and impulse noise without adding another weighting function. The range filter inside the bilateral filter switches between the Gaussian and impulse modes depending on the noise classification result. Simulation results show our noise detector has not only high noise detection rate but also high classification rate for both salt-and-pepper and
uniform impulse noise. Unlike the majority removing both type of mixed noise, the SBF achieves high PSNR and great image quality in removing salt-and-pepper, uniform and Gaussian noise.

[1] D. Sylvester and K. Keutzer, "A global wiring paradigm for deep submicron
design," IEEE Transactions on Computer-Aided Design, vol. 19, pp. 242-252,
Feb. 2000.
[2] C.M. Huang, C.M. Wu, C.C. Yang etc., "Implementation and prototyping of
a complex multi-project system-on-a-chip," IEEE International Symposium on
Circuits and Systems, pp. 2321-2324, May. 2009.
[3] Y. Zhao et al. ``Double sampling data checking technique: an online testing
solution for multisource noise-induced errors on chip interconnects and buses",
IEEE Trans on VLSI, vol. 12, no. 7, July 2004, pp. 746-755.
[4] M. Elgamel and M. Bayoumi, "Interconnect noise analysis and optimization in
deep submicron technology," IEEE Circuits and Systems Magazine, vol. 3, no.
4, pp. 6-17, 2003.
[5] C. Tomasi and R. Manduchi, "Bilateral filtering for gray and color images," in
Proc. IEEE International Conference on Computer Vision, pp. 839-846, 1998.
[6] T. Beukema, M. Sorna, K. Selander, S. Zier, B. L. Ji, P. Murfet, J. Mason, W.
Rhee, H. Ainspan, B. Parker, and M. Beakes, "A 6.4-Gb/s CMOS SerDes core
with feed-forward and decision-feedback equalization," IEEE Journal of Solid-
State Circuit, vol. 40, no. 12, pp. 2633-2645, Dec. 2005.
[7] Y. Guo, Z. Zhang, W. Hu, and L. Yang, "CMOS multiplexer and demultiplexer
for gigabit Ethernet," Proc. IEEE International Conference on Communications,
Circuits and Systems and West Sino Expositions, vol. 1, Chengdu, China, June
2002, pp. 819-823.
[8] K. Ishii, H. Nosaka, M. Ida, K. Kurishima, S. Yamahata, T. Enoki, T. Shibata,
and E. Sano, "4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication
systems," IEEE Transactions on Microwave Theory and Techniques,
vol. 51, no. 11, pp. 2181-2187, Nov. 2003.
[9] W. Garlepp, K. S. Donnelly, J. Kim, etc., "A portable digital DLL for high-speed
CMOS interface circuits," IEEE Journal of Solid-State Circuit, vol. 34, no. 5, pp.
632-644, May 1999.
[10] B. Razavi, "Monolithic phase-locked loops and clock recovery circuits: theory
and design," IEEE press, 1996.
[11] F.M. Gardner, "Charge-pump phase-lock loops," IEEE Transactions on Communication,
vol. COM-28, pp. 1849-1858, Nov. 1980.
[12] R.E. Best, "Phase-locked loops: theory, design and applications, New York:
McGraw-Hill, 1998.
[13] R.L. Aguitar and D.M. Santos, "Multiple target clock distribution with arbitrary
delay interconnects," IEE Electronic Letters., vol. 34, no. 22, pp. 2119-2120, Oct.
1998.
[14] R.B. Watson, Jr. and R. B. Iknaian, "Clock buffer chip with multiple target
automatic skew compensation," IEEE Journal of Solid-State Circuits, vol. 30,
no. 11, pp. 1267-1276, Nov. 1995.
[15] C.H. Kim et al, A 64-Mbit, "640-Mbyte/s bidirectional data strobed, double data rate SDRAM with a 40-mW DLL for a 256-Mbyte memory system," IEEE
Journal of Solid-State Circuits, vol. 33, no 11, pp. 1703-1710, Nov. 1998.
[16] Y. Moon, J. Choi, K. Lee, D.K. Jeong, and M.K. Kim, "An all-analog multiphase
delay-locked loop using a replica delay line for wide-range operation and low-jitter
performance," IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 377-384,
Mar. 2000.
[17] V. Soteriou and L.S. Peh, "Design-space exploration of power-aware on/off interconnection
networks," IEEE International Conference on Computer Design:
VLSI in Computers and Processors, Oct. 2004, pp. 510V517.
[18] A. R. Bharghava, M. B. Srinivas, "Transition Inversion based Low Power Data
Coding Scheme for Synchronous Serial Communication," IEEE Computer Society Annual Symposium on VLSI., pp. 103-108, 2009.
[19] S. Borkar, "Low power design challenges for the decade," Asia and South Pacific
Design Automation Conference, pp. 293-296, 2001.
[20] T. Sakurai, Design Challenges for 0.1um and Beyond," Asia and South Pacific
Design Automation Conference, pp. 553-558, 2000.
[21] M. R. Stan and W. P. Burleson, "Bus-Invert coding for Low-power I/O," IEEE
Transactions on VLSI systems, vol. 3, no. 1, pp. 49-58, Mar. 1995.
[22] Y. Shin, S. I. Chae, and K. Choi, "Partial Bus-Invert Coding for Power Optimization
of Application-Specific Systems," IEEE Transactions on VLSI systems,
vol. 9, no. 2, pp. 377-383, April 2001.
[23] R. B. Lin and C. M. Tsai, "Weight-based bus-invert coding for low-power applications,"
International Conference on VLSI Design, Jan. 2002, pp. 121-125.
[24] C. H. Kuo, W. B. Wu, Y. J. Wu, and J. H. Lin, "Serial Low Power Bus Coding
for VLSI," IEEE International Conference on Communications, Circuits and
Systems Proceedings, June 2006, pp. 2449-2453.
[25] P. Subrahmanya, R. Manimegalai, V. Kamakoti, and M. Mutyam, "A Bus Encoding
Technique for Power and Cross-talk Minimization," IEEE Conference on
VLSI Design, June 2004, pp. 443-448.
[26] M. Ghoneima and Y. Ismail, "Low Power Coupling-Based Encoding for On-Chip
Buses," IEEE International Symposium on Circuits and Systems, May 2004, pp.
325-328.
[27] A. Elkammar, N. Scheinberg, and S. Vemuru, "Bus Encoding Scheme to Eliminate
Unwanted Signal Transitions," IEEE International Workshop on Electronic
Design, Test and Applications, Jan. 2006, pp. 472-480.
[28] Z. Khan, T. Arslan, and A. T. Erdogan, "Low power system on chip bus encoding
scheme with crosstalk noise reduction capability," IEE Proceedings Computers
and Digital Techniques , vol. 153, no. 2, pp. 101-108, Mar. 2006.
[29] S. Vemuru, A. Elkammar, and N. Scheinberg, "Bus Encoding Schemes Using
Positive Correlated Switchings in Subbuses: A Comparison," IEEE, Midwest
Symposium on Circuits and Systems, Aug. 2008, pp. 213-216.
[30] M. Anders, N. Rai, R. K. Krishnamurthy, and S. Borkar, "A Transition-Encoded
Dynamic Bus Technique for High-Performance Interconnects," IEEE Journal of
Solid-State circuits, vol. 38, no. 5, pp. 709-714, May 2003.
[31] S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "A Coding Framework for Low-
Power Address and Data Busses," IEEE Transactions on VLSI systems, vol. 7,
no.2, pp. 212-221, June 1999.
[32] K. Lee, S. J. Lee and H. J. Yoo, "SILENT: Serialized Low Energy Transmission
Coding for On-Chip Interconnection Networks," IEEE International Conference
on Computer Aided Design, Nov. 2004, pp. 448-451.
[33] R. Abinesh , R. Bharghava and M. B. Srinivas, "Transition Inversion based
Low Power Data Coding Scheme for Synchronous Serial Communication," IEEE
Computer Society Annual Symposium on VLSI, May 2009, pp. 103-108.
[34] M. Ghoneima, Y. Ismail, M. Khellah, J. Tschanz, and V. De, "Serial-Link Bus:
A Low-Power On-Chip Bus Architecture," IEEE Transactions on Circuits and
Systems-I: Regular Papers., vol. 56, no. 9, pp. 2020-2032, Sept. 2009.
[35] P. P. Sotiriadis and A. Chandrakasan, "Bus energy minimization by transition
pattern coding (TPC) in deep submicron technologies," IEEE/ACM International Computer-Aided Design Conference, Nov. 2000, pp. 320-327.
[36] B. Razavi, "Challenges in the Design of High-Speed Clock and Data Recovery
Circuits," IEEE Communications Magazine, vol. 40, no. 8, pp. 94-101, Aug.
2002.
[37] Semiconductor Industry Association, Santa Clara, CA, "International Technology
Roadmap for Semiconductors," 2003.
[38] J. Cong, "An interconnect-centric design flow for nanometer technologies," IEEE
Proceedings, vol. 89, no. 4, pp. 505-528, Apr. 2001.
[39] C. Durkan and M. E. Welland, "Size effects in the electrical resistivity of polycrystalline nanowires," Physical Review. B, vol. 61, no. 20, pp. 14215-14218, May
2000.
[40] P. Gupta and A. Kahng, "Wire swizzling to reduce delay uncertainty due to
capacitive coupling," Proceedings of IEEE International Conference on VLSI
Design, Jan. 2004, pp. 431-436.
[41] Y. Shin and T. Sakurai, "Coupling-driven bus design for low-power applicationspeci
fic systems," Proceedings of Design Automation Conference (DAC), June
2001, pp. 750-753.
[42] A. B. Kahng, S. Muddu, E. Sarto, and R. Sharma, "Interconnect tuning strategies
for high performance ICs," Proceedings of the IEEE Conference on Design
Automation and Test in Europe (DATE), Feb. 1998, pp. 471-478.
[43] K. Hirose and H. Yasuura, "A bus delay reduction technique considering
crosstalk," Proceedings of the IEEE Conference on Design Automation and Test
in Europe (DATE), Mar. 2000, pp. 441-445.
[44] S. J. Lee, S. J. Song, K. Lee, J. H. Woo, S. E. Kim, B. G. Nam, and H. J. Yoo,
"An 800MHz Star-Connected On-Chip Network for Application to Systems on a
Chip," Technical Digest of IEEE International Solid-State Circuits Conference,
Feb. 2003, pp. 468-469.
[45] K. Lee, S. J. Lee and S. E. Kim, "A 51 mW 1.6 GHz on-chip network for
low-power heterogeneous SoC platform," IEEE International Solid-State Circuits
Conference, Feb. 2004, pp. 152-518.
[46] K. Lee, S. J. Lee and H. J. Yoo, "Low-Power Network-on-Chip for High- Performance
SoC Design," IEEE Transactions on VLSI system., vol.14, no.2, pp.
148-160, Feb. 2006.
[47] J. Kim, J. K. Kim, B. J. Lee, and D. K. Jeong, "Design Optimization of On-chip
Inductive Peaking Structures for 0.13um CMOS 40Gb/s Transmitter Circuits,"
IEEE Transactions on Circuits and Systems I, vol. 56, no. 12, pp. 2544-2555,
Dec. 2009.
[48] S. Kaeriyama, Y. Amamiya, H. Noguchi, Z. Yamazaki, T. Yamase, K. Hosoya,
M. Okamoto, S. Tomari, H. Yamaguchi, H. Shoda, H. Ikeda, S. Tanaka, T. Takahashi,
R. Ohhira, A. Noda, K. Hijioka, A. Tanabe, S. Fujita, and N. Kawahara,
"A 40 Gb/s multi-data-rate CMOS transmitter and receiver chipset with SFI-5
interface for optical transmission systems," IEEE Journal of Solid-State Circuits,
vol. 44, no. 12, pp. 3568-3579, Dec. 2009.
[49] N. Nedovic, A. Kristensson, S. Parikh, S. Reddy, S. McLeod, N. Tzartzanis, K.
Kanda, T. Yamamoto, S. Matsubara, M. Kibune, Y. Doi, S. Ide, Y. Tsunoda, T.
Yamabana, T. Shibasaki, Y. Tomita, T. Hamada, M. Sugawara, T. Ikeuchi, N.
Kuwata, H. Tamura, J. Ogawa, and W. Walker, "A 3 Watt 39.8-44.6 Gb/s Dual-
Mode SFI5.2 SerDes Chip Set in 65 nm CMOS," IEEE Journal of Solid-State
Circuits, vol. 45, no. 10, pp. 2016-2029, Oct. 2010.
[50] Jonathan E. Rogers and John R. Long, "A 10-Gb/s CDR/DEMUX With LC
Delay Line VCO in 0.18um CMOS," IEEE Journal of Solid-State Circuits, vol.
37, no. 12, pp. 1781-1789 , Dec. 2002.
[51] M. Sorna, T. Beukema, K. Selander, S. Zier, B. Ji, P. Murfet, J. Mason, W.
Rhee, H. Ainspan, and B. Parker, "A 6.4 Gb/s CMOS SerDes Core with feedforward
and decision-feedback equalization," IEEE International Solid-State Circuits Conference, Feb. 2005, pp. 62-63.
[52] C. F. Liao and S. I. Liu, "A 40 Gb/s CMOS Serial-Link Receiver With Adaptive
Equalization and Clock/Data Recovery," IEEE Journal of Solid-State Circuits,
vol. 43, no. 11, pp. 2492-2502, Nov. 2008.
[53] S. H. Lin and S. I. Liu, "Full-Rate Bang-Bang Phase/Frequency Detectors
for Unilateral Continuous-Rate CDRs," IEEE Transactions on Circuits and
Systems-II: Express Briefs, vol. 55, no. 12, pp. 1214-1218, Dec. 2008.
[54] Berkeley Predictive Technology Model: [On-line]. Available: http://ww-wdevice.
eecs.berkeley.edu/ptm
[55] C.M. Huang, C.M. Wu, C.C. Yang etc., "Implementation and prototyping of
a complex multi-project system-on-a-chip," IEEE International Symposium on
Circuits and Systems, pp. 2321-2324, May. 2009.
[56] C.M. Huang, K.J. Lee, C.C. Yang etc., "Multi-Project System-on Chip (MPSoC):
A Novel Test Vehicle for SoC Silicon Prototyping," IEEE SoC Conference, pp.
137-140, Sept. 2006.
[57] C.M. Huang, C.M. Wu, C.C. Yang etc., "PrSoC: Programmable System on-Chip
(SoC) for Silicon Prototyping," IEEE International Symposium on Circuits and
Systems, pp. 3382-3385, May. 2008.
[58] ABMA 2 Specification, http://www.arm.com/products/solutions/AMBASpec/html
[59] Y.H. Hsu, M.H. Lu, P.L. Yang, and F.T. Chen etc., "A 28Gbps 44 switch with
low jitter SerDes using area-saving RF model in 0.13um CMOS technology,"
IEEE International Symposium on Circuits and Systems, pp. 3086-3089, May.
2008.
[60] M.V. Lau, S. Shieh, P.F. Wang etc., "Gigabit Ethernet switches using a shared
buffer architecture," IEEE Communications Magazine, vol.41, issue 12, pp. 76-
84, Dec. 2003.
[61] J.J. Olmos and R. Agusti, "Performance analysis of a second order delay-lock
loop with application to a CDMA system with multipath propagation," IEEE
ICUPC Proceedings, pp. 08.04/1 - 08.04/5, Sept. 1992.
[62] Y. Moon, J. Choi, K. Lee, D. K. Jeong and M. K. Kim, "An All-Analog Multiphase
Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation
and Low-Jitter Performance," IEEE Journal of Solid-State Circuits, vol.35, no.3,
pp. 377-384, Mar. 2000.
[63] T. Liu, and C. Wang, "A 1-4 GHz DLL based low-jitter multi-phase clock generator
for low-band ultra-wideband application," IEEE Asia-Pacific Conference
on Advanced System Integrated Circuits, pp. 330-333, Aug. 2004.
[64] R.M. Weng, T.H. Su, C.Y. Liu, and Y.F. Kuo, "A CMOS Delay-Locked Loop
Based Frequency Multiplier for Wide-range Operation, " IEEE International
Conference on Electron on Devices and Solid-State Circuit, pp. 419-422, 2005.
[65] G. Chien and P.R. Gray, "A 900-MHz local oscillator using a DLL-based frequency
multiplier technique for PCS applications," IEEE Journal of of Solid-
State Circuits, vol. 35, pp. 1996-1999, 2000.
[66] S. Badel and Y. Leblebici, "Breaking the Power-Delay Tradeoff Design of Low-
Power High-Speed MOS Current-Mode," IEEE International Symposium on Circuits and Systems, pp. 1871-1874, May. 2007.
[67] K.H. Cheng, C.L. Hung, and C.W. Su, "A Sub-1V Low-Power High-Speed Static
Frequency Divider," IEEE International Symposium on Circuits and Systems,
pp. 3848-3851, May. 2007.
[68] H.J. Hsu, and C.T. Chiu, and Y.S. Hsu, "Design of ultra low power current mode
logics with adaptive body bias," IEEE ISSOC, pp. 141-144, Sept. 2007.
92
[69] L. Li, J. H.M. Chen, R.C. Chang, "A Low Jitter Delay-Locked Loop with a
Realignment Duty Cycle Corrector," IEEE ISOCC, pp. 75-76, Sept. 2005.
[70] P. Heydari and M. Pedram, Jitter-induced power/ground noise in CMOS PLLs:
a design perspective," IEEE Computer Design, pp. 209-213, Sept. 2001.
[71] H. Chang, J. Lin, C. Yang, and S. I. Liu, "A wide-range delay-locked loop with
a fixed latency of one clock cycle," IEEE Journal of Solid-State Circuits, vol.37,
no.8, pp. 1021-1027, Aug. 2002.
[72] M.S. Kao, C.H. Jen, C.T. Chiu, etc., "A 10 Gb/s Wide-Band Current-Mode
Logic I/O Interface for High-Speed Interconnect in 0.18um CMOS Technology,"
IEEE ISSOC, pp. 257-260, Sept. 2005.
[73] W. Garlepp, K. S. Donnelly, J. Kim, etc., "A portable digital DLL for high-speed
CMOS interface circuits," IEEE Journal of Solid-State Circuits, vol. 34, no. 5,
pp. 632-644, May 1999.
[74] D.G. Lin, B,H. Lu and H. Chiueh, "An 100MHz to 1.6GHz DLL-Based Clock
Generator Using a Feedback-Switching Detector," IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC 2010), Sept., 2010.
[75] H. H Chang, R.J Yang, and S.I. Liu, Low jitter Butterworth Delay-Locked
Loops," IEEE VLSI. Circuit, pp. 177-180, Jun. 2003
[76] K. Jabeom, et al. "A Low-Power Programmable DLL-Based Clock Generator
With Wide-Range Anti-harmonic Lock," IEEE Transactions on Circuits and
Systems II: Express Briefs, vol. 56, pp. 21-25, 2009.
[77] C.H. Lin, and C.T. Chiu, "A 2.24GHz Wide Range Low Jitter DLL-Based Frequency
Multiplier using PMOS Active Load for Communication Applications ,"
IEEE International Symposium on Circuits and Systems, pp. 3888-3891, May.
2007.
[78] C. Tomasi and R. Manduchi, "Bilateral filtering for gray and color images," in
Proc. IEEE International Conference on Computer Vision, pp. 839-846, 1998.
[79] H. Lin and A. N. Willson Jr., "Median filters with adaptive length," IEEE Trans-
actions on Circuits System, vol. 35, no. 6, pp. 675-690, Jun. 1988.
[80] S.J. Ko and Y.H. Lee, "Center weighted median filters and their applications to
image enhancement," IEEE Transactions on Circuits Syst., vol. 38, no. 9, pp.
984-993, Sep. 1991.
[81] R.C. Hardie and K.E. Barner, "Rank conditioned rank selection filters for signal
restoration," IEEE Transactions on Image Process., vol. 3, no. 3, pp. 192-206,
Mar. 1994.
[82] G. Pok, J.C. Liu, and A.S. Nair, "Selective removal of impulse noise based on
homogeneity level information," IEEE Transactions on Image Process., vol. 12,
no. 1, pp. 85-91, Jan. 2003.
[83] R. Garnett, T. Huegerich, C. Chui, and W. He, "A universal noise removal
algorithm with an impulse detector," IEEE Transactions on Image Process.,
vol. 14, no. 11, pp. 1747-1754, Nov. 2005.
[84] N.I. Petrovic and V. Crnojevic, "Universal impulse noise filter based on genetic
programming," IEEE Transactions on Image Process., vol. 17, no. 7, pp. 1109-
1120, Jul. 2008.
[85] E. Abreu, M. Lightstone, S. K. Mitra, and K. Arakawa, "A new efficient approach
for the removal of impulse noise from highly corrupted images," IEEE
Transactions on Image Process., vol. 5, no. 6, pp. 1012-1025, Jun. 1996.
[86] T. Chen and H.R. Wu, "Adaptive impulse detection using center-weighted median
filters," IEEE Signal Process. Lett., vol. 8, no. 1, pp. 1-3, Jun. 2001.
[87] Y. Dong and S. Xu, "A new directional weighted median filter for removal of
random-valued impulse noise," IEEE Signal Process. Lett., vol. 14, no. 3, pp.
193-196, Mar. 2007.
[88] S. Peng and L. Lucke, "Multi-level adaptive fuzzy filter for mixed noise removal,"
in Proc. IEEE Int. Symp. Circuits Systems, vol. 2, Seattle, WA, pp. 1524-1527,
Apr. 1995.
[89] M. Zhang and Bahadir K. Gunturk, "Multiresolution Bilateral Filtering for Imgage
Denoiseing," IEEE Transactions on Image Process., vol. 17, no. 12, pp.
2324-2333, Dec. 2008.
[90] S. Schulte, M. Nachtegael, V. De Witte, D. Van der Weken, and E.E. Kerre, "A
fuzzy impulse noise detection and reduction method," IEEE Transactions on
Image Process., vol. 15, no. 5, pp. 1153-1162, May. 2006.
[91] T. Chen, K.K. Ma, and L.H. Chen, "Tri-state median filter for image denoising,"
IEEE Transactions on Image Process., vol. 8, no. 12, pp. 1834-1838, Dec. 1999.
[92] T. Sun and Y. Neuvo, "Detail-preserving median based filters in image processing," Pattern Recognit. Lett., vol. 15, pp. 341-347, Apr. 1994.
[93] Z. Wang and D. Zhang, "Progressive switching median filter for the removal of
impulse noise from highly corrupted images," IEEE Transactions on Circuits
System-II, Analog Digit. Signal Process., vol. 46, no. 1, pp. 78-80, Jan. 1999.
[94] P.E. Ng and K.K. Ma, "A switching median filter with boundary discriminative
noise detection for extremely corrupted images," IEEE Transactions on Image
Process., vol. 15, no. 6, pp. 1506-1516, Jun. 2006.
[95] K.S. Srinivasan and D. Ebenezer, "A new fast and efficient decision-based algorithm for removal of high-density impulse noises," IEEE Signal Process. Lett.,
vol. 14, no. 3, pp. 189-192, Mar. 2007.
[96] V. Crnojevic, "Impulse noise filter with adaptive MAD-based threshold," in
IEEE International Conference on Image Processing, pp. 337-340., Mar. 2005.
[97] R.H. Chan, C.W. Ho, and M. Nikolova, "Salt-and-pepper noise removal by
median-type noise detectors and detail preserving regularization," IEEE Trans-
actions on Image Process., vol. 14, no. 10, pp. 1479-1485, Oct. 2005.
[98] H. Hwang and R.A. Haddad, "Adaptive median filters: new algorithms and
results," IEEE Transactions on Image Process., vol. 4, no. 4, pp. 499-502, Apr.
1995.
[99] H. Xu, G. Zhu, F. Peng, and D. Wang, "Adaptive fuzzy switching filter for
images corrupted by impulse noise," Pattern Recognit. Lett., vol. 25, pp. 1657-
1663, 2004.
[100] N. Alajlan, M. Kamel, and E. Jernigan, "Detail preserving impulsive noise
removal," Signal Process.: Image Commun., vol. 19, pp. 993-1003, 2004.
[101] P.S. Windyga, "Fast impulsive noise removal," IEEE Transactions on Image
Process., vol. 10, no. 1, pp. 173-179, Jan. 2001.
[102] D. Van De Ville, M. Nachtegael, D. Van der Weken, E. E. Kerre, W. Philips,
and I. Lemahieu, "Noise reduction by fuzzy image filtering," IEEE Transactions
on Fuzzy Syst., vol. 11, no. 4, pp. 429-436, Aug. 2003.
[103] T. Chen and H.R. Wu, "Space variant median filters for the restoration of
impulse noise corrupted images," IEEE Transactions on Circuits and Systems
II, vol. 48, no. 8, pp. 784-789, 2001.
[104] W.K. Pratt, Digital image processing, John Wiley and Sons, N.Y., 1978.
[105] I. Pitas and A.N. Venetsanopoulos, "Nonlinear mean filters in image processing," IEEE Transactions on Acoustics, Speech, Signal Processing, vol. ASSP-34,
no. 3, pp. 573-584, June 1986.
[106] I. Pitas and A.N. Venetsanopoulos, Nonlinear Digital Filters: Principles and
Applications. Boston, MA: Kluwer Academic Publishers, 1990.
[107] I. Pitas and A.N. Venetsanopoulos, "Order statistics in digital image processing,"
Proc. IEEE, vol. 80, no. 12, pp. 1893-1921, Dec. 1992.
[108] A.K. Jain, Fundamentals of Digital Image Processing, Prentice Hall Information
and System Sciences Series, 1989.
[109] M. Elad, "On the Origin of the Bilateral Filter and Ways to Improve It," IEEE
Transactions on Image Processing, vol. 11, no. 10, pp. 1141-1151, Oct. 2002.