隨著超大型積體電路的複雜度愈來愈高，以及電源供應網路的電流密度持續增加，使得電源供應電壓的壓降(IR drop)問題日益嚴重，而這個問題會造成整個電路性能的降低。現今用於估算電源電壓壓降(或電源供應雜訊)的電源模型多半因為忽略輸入樣式、元件電流波形以及元件位置而使得其準確性不足，或者其方法需要耗費太多的時間。在本論文中，我們提出一個建立於元件電流波形特性的電源格網分析方法來估算電源電壓的壓降。在實作上，我們會藉由HSPICE的模擬來建立一個元件特性庫用以儲存各個元件於不同輸入樣式時的延遲、斜率以及電流波形。再者，在邏輯模擬以及元件特性指派後，我們會考慮每個元件波形及其位於電源網路上的位置來決定代表每個元件的電流源為何。最後，我們會利用一個一階疊代法去估算在電源網路上的最大電壓壓降。此外，由於電源壓降會影響元件原本的延遲，因此我們的方法有個迴授迴圈，並於其中利用更新過的元件延遲來重新計算電源上的壓降。根據實驗數據顯示，我們的模擬器的速度至少比現今常見的電路層級模擬軟體Nanosim快上10000倍，且平均誤差僅僅只有7.98%。另外，我們也會展現電壓壓降在掃瞄測試以及隨機樣式模擬的壓降估算及最長路徑電路延遲增加率於不同電源網路品質下之實驗結果。

IR drop has become a critical issue recently because of the increase in the circuit size and supply
current density, and it will degrade the circuit performance. The present power models for IR
drop (or power supply noise) estimation usually lack accuracy due to neglect of input patterns, cell
current waveform and cell location, or they cost too much time for larger circuits. In this thesis, we
propose a power grid analysis method based on cell current waveform characterizations to estimate
the maximum IR drop. In the process, we create the cell characterization library considering delay,
slope, and current waveform with different input patterns by HSPICE simulation. Furthermore, we
consider each cell current waveform and cell location to determine the current source for each cell
after logic simulation and cell characterization assignment. Finally, we use a first-order iterative
method to calculate the maximum IR drop in the power network. Additionally, our method has
an extra feedback loop to recalculate the IR drop by the modified cell delay because IR drop will
affect the original cell delay. The experimental results show that our simulator is at least 10000
times faster than Nanosim, a common circuit-level simulator, and the average error is only about
7.98%. In addition, we also show the results of maximum IR drop estimation and longest path
delay increase for scan test and random pattern simulation by different qualities of power network.

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