The continuing advances in digital designs create a significant challenge to design verification which is known to be one of the most time-consuming processes of the whole design flow. Previous work successfully generate effective stimuli for detecting gate level design errors, whereas the Register-Transfer Level (RTL) design errors do not take into consideration due to its complication. This paper presents a new approach to detect the modeled RTL design errors which occur frequently. A new representation ``Tsing-Hua Verification Format'' (THVF) for effectively modeling those design errors is also presented. As a result, the design errors can be modeled as single stuck-line faults on the THVF representation. In this way, the stimuli for detecting the faults can be automatically generated such that the corresponding design errors can be detected.

由於目前數位設計日趨複雜，因此在驗證的工作上成為在設計的流程中主要的挑戰，且驗證的工作以成為在整個設計流程中最花費時間的一項工作。前人的研究已經成功為邏輯閘層的設計錯誤產生有效的激勵。但是由於暫存器轉換層級設計錯誤遠比邏輯閘層的設計錯誤來的複雜所以之前的研究都不考慮暫存器轉換層級設計錯誤。這篇研究提出一種新的方式來有效的將常見了暫存器轉換層級的設計錯誤模型化。並且也提出一種新型的驗證格式(THVF)以有效的將其暫存器轉換層級的錯誤模型化。因此，我們可以有效的且自動的產生暫存器轉換層級的錯誤的激勵，而所對應到的暫存器轉換層級的錯誤就可以在驗證的過程中被偵測到。

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