隨著半導體製程的演進，單一晶片上能包含的電晶體數目正以飛快的速度成
長中，製造一個擁有數百萬甚至千萬顆電晶體的晶片再也不是遙不可及的事情。現在超大型積體電路的技術讓我們有辦法將一整個系統放入單一的晶片中，這就是所謂的系統型晶片 (System-on-Chip)。設計一個系統晶片是非常困難而通常會消耗大量的人力以及設計時間，所以現在實踐系統型晶片時，設計者通常使用所謂的矽智財 (Silicon Intellectual Property)來建構整個系統晶片。在這個利用現存的矽智財來建構系統晶片的方法下，在量產前也產生了新的測試課題。主要的課題就是所謂的矽智財的設計者需要提供設計以及測試的資訊給矽智財的使用者，讓使用者可以順利的在重建整個測試在量產前。IEEE 1500 規範了一個測試包裝的架構 (Wrapper Architecture)來提供標準的測試介面，IEEE 1450.6 則規定了標準的測試資料表示方法。這兩個介面提供了重建測試的困難度也降低了設計系統晶片的難度。
另外由於晶片的時脈越來越快，所以設計者在設計晶片時必須要更準確的考
慮時脈的問題，所以延遲錯誤測試在近幾年越來越受到重視。所以在這篇論文中
提出了處理延遲錯誤測試和IEEE 1500 包裝架構之間溝通問題的一個測試流程控制器。這個測試流程控制器可以支援平行測試，藉由在測試流程中加入平行測
試，可以達到節省測試時間的目的並進一步達成節省測試成本的目的。另外為了
支援測試流程控制器的需要，這篇論文同時提出了一個時脈控制器。藉由兩個控
制器的互相作用達成平行測試的目標。在這篇論文的最後以一顆現存的系統晶片
來做實驗來驗證我們的測試流程控制器是可用的並且不會對測試率造成引響。

Abstract
In order to reduce design time, the reusable IP cores become primary design trend. Issue about delay fault testing becomes more important because of the high performance requirement in VLSI chip. To achieve high performance, VLSI chips need to work correctly at the rated clock. The IEEE 1500 standard provides a standard test interface, and the IEEE 1450.6 standard defines the way to reuse test information. Cooperating with IEEE 1450.6, the IEEE 1500 makes the testing of pre-design IP based SOC easier. In this thesis, a clock controller and a test controller are proposed to support multiple delay testing and to communicate the clock controller and the IEEE 1500 wrapper, respectively. The experimental result shows acceptable area overhead of 0.3% compared with modern SOC, and test time is reduced about 25% when applying parallel test without any test coverage loss.

[1] H.F. Ko and Nicola Nicolici, “Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing,” Proc. of Asian Test Symposium, pp. 454-459, Nov. 2004.

[2] S. Wang et al., “Hybrid delay scan: A Low Hardware Overhead Scanbased Delay Test Technique for High Fault Coverage and Compact Test Sets,” Proc. of DATE, pp.1296-1301, 2004.

[3] Arabi, K., Ihs, H., Dufaza, C. and Kaminska, B., “Digital Oscillation test method for delay and stuck-at fault testing of digital circuit,” Proc. of International Test Conf., pp. 91-100, 1998.

[4] Vermaak, H.J. and Kerhoff, H.G., “Using the oscillation test method to test for delay faults in embedded cores,” Proc. of Africon Conf., Vol. 2, pp. 1105-1110, 2004.

[5] Vermaak, H.J. and Kerhoff, H.G., “Enhanced P1500 compliant wrapper suitable for delay fault testing of embedded cores,” Proc. of European Test Workshop, pp. 121-126, 2003.

[6] “IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data— Core Test Language (CTL),” http://ieeexplore.ieee.org/servlet/opac?punumber= 10764.

[7] “IEEE Standard Testability Method for Embedded Core-based Integrated Circuits,” http://ieeexplore.ieee.org/servlet/opac?punumber=10075

[8] H.H. Chiu, P.L. Chen, C.Y. Li, and T.Y. Chang, “A Delay Test Wrapper Design on Core-Based System-on-Chip” Proc. of VLSI/CAD symp., pp. P2-62, 2005.

[9] I.ARM Components, “AMBA Specification Rev 2.0”, May 1999.

[10] ARM Components, Inc., “Multi-Layer AHB,” 2001.

[11] C.P. Su, T.F. Lin, C.T. Huang and C.W. Wu, “A high-throughput low-cost AES processor,” IEEE Communications Magazine, Vol. 41, pp. 86-91, 2003.

[12] M.Y. Wang, C.P. Su, C.T. Huang and C.W. Wu, “A HMAC processor with integrated SHA-1 and MD5 algorithms,” Proc. of Asia and South Pacific Design Automation Conf., pp.456-458, 2004.

[13] M.C. Sun, C.P. Su, C.T. Huang and C.W. Wu, “Design of a scalable RSA and ECC crypto-processor,” Proc. of Asia and South Pacific Design Automation Conf., pp. 495-498, 2003.

[14] C.W Wang, J.R. Huang, K.L. Cheng, H.S. Hsu, C.T. Huang, C.W. Wu and Y.L. Lin, “A test access control and test integration system for system-on-chip,” in Proc. of Sixth IEEE Int. Workshop on Testing Embedded Core-Based System-Chips (TECS), pp. P2.1 – P2.8, 2002.

[15] Synopsys, Inc. “TetraMax ATPG User Guide”, Version U-2003.06, June 2003.