Design and implementation of folded and Multi-rack Multi-rate supported Load Balancing Birkhoff-von Neumann switches part(2)-Linecard

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研究生：	蘇敬閔 Su, Ching Min
論文名稱：	Design and implementation of folded and Multi-rack Multi-rate supported Load Balancing Birkhoff-von Neumann switches part(2)-Linecard 支援多層級、多重速率之折疊式負載平衡布可夫馮紐曼交換機之設計與實作 part(2)-線卡
指導教授：	李端興 Lee, Duan-Shin
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2009
畢業學年度：	97
語文別：	中文
論文頁數：	51
中文關鍵詞：	交換機
外文關鍵詞：	switch
相關次數：	點閱：2 下載：0
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在現今日益龐大的網路中，封包的傳遞會遭遇到三個重大問題，Routing Table過於龐大、shortest path congestion、以及multi-rate時無法充分利用頻寬，而針對這些問題CISCO提出了CRS-1 solution，此為一個1對16的兩層式架構，但此架構採用了配對(matching)的交換模式:i-SLIP，可擴充性並不佳，導致其交換機受限於兩級16個埠的規模，而現在經由我們實作證實以負載平衡布可夫馮鈕曼交換機為藍圖的架構是可行的，它擁有100%交換效能、低複雜度、高擴充性的特性，且經由我們的設計改良後，可進一步支援Multi-Rack-Multi-Rate，因此上述的問題，在把我們的架構擴展到網路中時，將可得到比用CRS-1 solution更大的改善，也由於市場中尚未出現以負載平衡布可夫馮鈕曼交換機為藍圖的相關產品，在我們的prototype實作成功後，期望能讓更多的研究團隊對此架構產生興趣，一同投入研究，使此交換機的設計更趨完善，成為下一代的主流交換機。

Contents
序言    I
摘要    II
CONTENTS    IV
FIGURES    VI
CHAPTER1  MOTIVATION AND INTRODUCTION    1
1.1 INTRODUCTION    1
CHAPTER2  FEATURES AND INNOVATION OF OUR DESIGN    3
2.1 TREE TOPOLOGY MULTIPLEXED MULTI-RACK STDM SWITCHING NETWORK CONSTRUCTION    4
2.2 PORT REMAPPING FUNCTION TRANSLATION    4
2.3 MULTI-RATE SUPPORTED AGGREGATED STDM    4
2.4 MULTI-STAGE FOLDED ARCHITECTURE    5
2.5 FAULT-TOLERANT SWITCH ARCHITECTURE    5
CHAPTER3  CHALLENGES AND DESIGN SOLUTIONS    7
3.1 CHALLENGES    7
3.1.1 Rate aggregated constructure    7
3.1.2 Routing table complexity    7
3.1.3 Shortest path conjestion    8
3.2 DESIGN SOLUTIONS    9
3.2.1 Folded Load-balanced Birkhoff-von Neumann Switch    9
3.2.3 Recursive STDM Construction    9
3.2.4 Port remapping    10
3.2.5 Rate Aggregated Architecture    15
3.2.6 STDM Connection Pattern    20
CHAPTER 4 SYSTEM ARCHITECTURE    24
4.1 ASSUMPTION    25
4.2 SYSTEM OPERATION    26
4.2.1 VIQ Buffer    27
4.2.2 Rate-aggregated STDM & Embedded STDM    27
4.2.3 First Stage Switch    27
4.2.4 VOQ Buffer    28
4.2.5 Second Stage Switch    28
4.2.6 Re-sequencing Buffer    29
CHAPTER 5 VIRTUAL INPUT QUEUE, EMBEDDED STDM & RATE-AGGREGATED STDM    30
Hardware platform    30
Software environment    30
5.1 MAIN ARCHITECTURE    31
5.2 LINE CARD DESIGN    32
5.2.1 Virtual Input Queue & Embedded STDM    34
5.2.2 Aggregated STDM    37
5.2.3 Queue Manager    38
5.2.4 Virtual Output Queue    39
5.2.5 Resequencing buffer    44
5.2.6 Buffer Manager    45
CHAPTER 6 CONCLUSION AND FUTURE WORK    49
REFERENCE    50

                                

Reference

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[15] Design and Implementation of Folded and Multi-rack, Multi-rate Supported
Load-Balancing Birkhoff-von Neumann Switches part(1)-Core Switch

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