近年來，由於平面顯示器和通訊產品的推陳出新，使得功率元件的需求大幅增加，而投入這方面的人才亦有成長的趨勢，倘若能配合國內成熟之半導體產業基礎，順應國際科技發展的潮流，將功率元件整合成智慧型功率積體電路，則這個領域的發展將有長足的進步。為了順應電路積體化的潮流，將功率元件與低壓電路整合在同一晶片上，傳統垂直式的元件結構必須改成橫向式的設計，而這之中最常使用的元件，分別為LDMOSFET和LIGBT。
應用RESURF(Reduced Surface Field，簡稱RESURF)的原理，可以將橫向式的功率元件做在薄磊晶層上，使得電路的積體化變為可行，但元件電性對製程參數的改變非常敏感，導致元件的設計更加困難。傳統垂直式DMOSFET高導通電阻的缺點在LDMOSFET中依舊存在，而垂直式IGBT關閉延遲和閂鎖的現象，也在LIGBT中發生。如何製作一個省電、耐壓、快速的功率元件，將是一個重要的課題。

目前，最受大家歡迎的顯示器產品為電漿平面顯示器(Plasma Display Panel，簡稱PDP)，其驅動IC使用的電壓約200V。因此，本篇論文即以200V高壓元件為設計的目標，利用Tsuprem4和Medici等模擬軟體，分別模擬LDMOSFET和LIBGT的結構，分析元件關閉和導通的特性，討論各種改進元件缺點的方法，將一些可行的技巧應用於BCD製程，使元件可以被實際的製作和生產，並達到最佳化的設計。

In recent years, following the introducing of state of the art flat panel displays and communication products, demands for power devices have risen substantially. In keeping with the trend of circuit integration, traditional vertical device needs to be changed to lateral structure to make it possible for the integration of power devices and low voltage circuit on the same chip. The most commonly used lateral power devices are LDMOSFET and LIGBT.
Applying the principles of Reduced Surface Field (RESURF), integration of circuits can be realized by building power devices on a thin epi-layer. It is worth noting that device designs are complicated by the high sensitivity of device electrical characteristics to changes in process parameters. Problems with high on-resistance that are seen in traditional vertical structure DMOSFET still appear in LDMOSFET and phenomena of turn-off delay and latch-up are seen in LIGBT as well. Thus, designing a low power consumption, high breakdown, and high speed device is a significant topic for discussion.

At present, the most promising display, the Plasma Display Panel (PDP) employs a driver IC, which requires a voltage of around 200V. The subject for this thesis would thus be the design of a 200V power device. This study would center on simulations of the structures of LDMOSFET and LIBGT with tools like Tsuprem4 and Medici, analyses of turn-off and turn-on characteristics of the device, discussions on methods of overcoming defects in the device, and applications of certain workable techniques on BCD process to actually fabricate a device of an optimal design.

[1] B. J. Baliga, “An overview of smart power technology”, IEEE Trans. Electron Devices, Vol. ED-38, pp. 1568-1575, July 1991
[2] Kenya Kobayashi, Hiroshi Yanagigawa, Kazuhisa Mori, Shuichi Yamanaka, Akira Fujiwara, “High voltage SOI CMOS IC technology for driving plasma display panels”, ISPSD '98, pp. 141-144
[3] Min Liu, C. A. T. Salama, P. Schvan and M. King, “A fully resurfed, BiCMOS-compatible, high voltage MOS transistor”, ISPSD '96, pp. 143-146
[4] A. W. Ludikhuize, “Design aspect of high voltage devices for a 700-1200V IC process”, Proc. Symp. on High Voltage and Smart Power ICs, pp. 133-138, 1989
[5] P. Ratnam, “Novel silicon-on-insulator MOSFET for high-voltage integrated circuits”, Electronics Letters, Vol. 25, No. 8, pp. 536-537, April 1989
[6] J. G. Mena, and C. A. T. Salama, “High-voltage multiple-resistivity drift-region LDMOS”, Solid-State Electronics, Vol. 29, No. 6, pp. 647-656, 1986
[7] Serag E. D. Habib, “The ALDMOST: a new power MOS transistor”, IEEE Trans. Electron Device, Vol. ED-8, No. 6, pp. 257-259, Jun. 1987
[8] Mueng-Ryul Lee and Oh-Kyong Kwon, “High performance extended drain MOSFETs (EDMOSFETs) with metal field plate”, ISPSD '99, pp. 249-252
[9] Shuming Xu, Yuanzheng Zhu, Pang-Dow Foo, Yung C. Liang, and Johnny. K. O. Sin, “Folded gate LDMOS with low on-resistance and high transconductance”, ISPSD '2000, pp. 55-58
[10] Sung-Lyong Kim, Hoie-Yoon Yang and Yearn-Ik Choi, “A low on-resistance SOI LDMOS using a recessed source and a trench drain”, Proc. 22nd International Conference on Microelectronics, Vol 2 , pp. 641-644, 1999
[11] Andrew L. Robinson, Deva N. Pattanayak, Michael S. Adler, B. J. Baliga, and Eric J. Wildi, “Lateral insulated gate transistors with improved latching characteristics”, IEEE Electron Device Letters, Vol EDL-7, No. 2, pp. 61-63, 1986
[12] Azzouz Nezar, Philip K. T. Mok and C. Andre T. Salama, “Latch-up prevention in insulated gate bipolar transistors”, ISPSD '93, pp. 236-239
[13] Jun Cai and Keng Foo Lo, “A latch-up immunized lateral trench-gate conductivity modulated power transistor”, Proc. of 7th IPFA '99, Singapore, pp. 168-172
[14] T. Paul Chow, B. J. Baliga, Deva N. Pattanayak, Michael S. Adler, “Comparison of p-channel lateral insulated-gate bipolar transistors with and without collector shorts”, IEEE Electron Device Letters, Vol. 11, pp. 184-186, 1990
[15] Johnny K. O. Sin, and Satyen Mukherjee, “Lateral insulated-gate bipolar transistor (LIGBT) with a segmented anode structure”, IEEE Electron Device Letters, Vol. 12, No. 2, pp. 45-47, Feb. 1991
[16] J. K. O. Sin, C. A. T. Salama, and L. Z. Hou, “Analysis and characterization of the hybrid Schottky injection field effect transistor”, IEDM Tech. Dig., 1986, pp.222
[17] B. J. Baliga, Modern Power Devices, Copyright 1987 by John Wiley & Sons, pp. 233-236
[18] J. A. Appeals, and H. M. J. Vaes, “High-voltage thin layer devices (RESURF devices)”, IEDM Tech. Dig., pp. 238-239, 1979
[19] Zahir Parpia, and C. Andre T. Salama, “Optimization of RESURF LDMOS transistors: an analytical approach”, IEEE Electron Device, Vol. ED-37, No. 3, pp. 789-795, March 1990
[20] Tadanori Yamaguchi and Seiichi Morimoto, “Process and device design of a 1000-V MOS IC”, IEEE Trans. Electron Devices, Vol. ED-29, No. 8, pp. 1171-1178, August 1982
[21] Yeong-Seuk Kim, Jerry G. Fossum, and Richard K. Williams, “New physical insights and models for high-voltage LDMOST IC CAD”, IEEE Trans. Electron Devices, Vol. 38, No. 7, pp. 1641-1648, July 1991
[22] S. Musumeci, A. Raciti, M. Sardo, F. Frisina, R. Letor, “PT-IGBT PSpice model with new parameter extraction for life-time and epy dependent behaviour simulation”, PESC '96, pp. 1682-1688
[23] Mark R. Simpson, “Analysis of negative differential resistance in the I-V characteristics of shorted-anode LIGBT’s”, IEEE Trans. Electron Devices, Vol. 38, No. 7, pp. 1633-1639, July 1991