高解析度低輸出電壓漣漪的數位式脈波寬度調變控制直流降壓器

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研究生：	李祐旻 Li, You-Min.
論文名稱：	高解析度低輸出電壓漣漪的數位式脈波寬度調變控制直流降壓器 A novel high-resolution and low-ripple digitally controlled PWM for DC-DC buck converter
指導教授：	張彌彰 Chang, Mi-Chang
口試委員:	徐永珍 Hsu, Yung-Chen 盧向成 Lu, Hsiang-Cheng
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2020
畢業學年度：	108
語文別：	英文
論文頁數：	106
中文關鍵詞：	數位脈寬調變、直流-直流、降壓器、數位控制、低漣波、高解析度
外文關鍵詞：	DPWM, DC-DC, buck converter, digital control, low ripple, high resolution
相關次數：	點閱：2 下載：0
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直流-直流轉換器是現今移動電子設備中的重要元件，因為它可以將電池的電源轉換成不同電壓值，以符合當今應用電子產品的需求。為了延長電池的續航力，此轉換器應採用單晶片實現且需產生準確的輸出電壓、較小的電壓漣波、較高的轉換效率以及較小的功率消耗和面積，從而增強系統性能並降低成本。
在DC-DC轉換器設計的不同方法中，數位脈衝寬度調製（DPWM）是最近先進電源管理的研究重點之一，因為其具有以下幾點優點：易於設計、可使用現有的數位設計流程、容易轉換至下世代半導體製程、較小的面積以及較低的功率消耗。為了提高輸出電壓的解析度並抑制輸出電壓的漣波，DPWM電路通常需要較大的位元數目來實現。但是，使用較大的位元數目會增加電壓轉換器的功率消耗和面積，因而降低DPWM技術的實用性。
在本文中，為了不要直接實現較大位元數目的硬體，我們提出了一種新的方法來提高有效位元數目。如此一來，既有大位元數目架構的優點，並同時保持較小的功率消耗和面積。本文所提出的方法綜合Dither方法和RC方法的概念，通過額外控制電路達成精確地調控脈衝寬度。本文也描述了如何設計並實現此控制電路，以一個3位元DPWM轉換器產生有效5位元的輸出電壓準位。此外，我們也以模擬的方式與其他文獻中的轉換器進行比較，證明此方法的優越性，即使我們使用的是較成熟的半導體技術，比較結果也顯示我們的方法在各種性能指標上的優勢。

DC-DC converter is a key in modern mobile electronic device since it can covert the power supply of a single battery to different voltage levels that are needed in today’s applications. To minimize battery recharging time, enhance system performance and reduce cost, an on-chip DC-DC converter should be designed to produce accurate voltage level, small ripple, high conversion efficiency and small power consumption and area.
Among different approaches for DC-DC converter design, Digital Pulse-Width-Modulation (DPWM) is one of the focuses in recent researches, due to ease of design, available digital design flow and good scalability to small area and power for advanced technologies. To improve output voltage resolution and inhibit output ripple, large number of bits are usually required. This large number of bits, however, increased the power consumption and area of the converter, and reduce the attractiveness of the DPWM approach.
In this thesis, we proposed a novel approach to improve the effective number of bits without actually implementing the extra bits, thus taking the advantages of large bits while maintaining small power and area. It is achieved by adding extra control circuits to modify the pulse width accurately, using both Dither method and RC method. The design and implementation of control circuit enables a 3-bit DPWM converter to produce 5-bit effective output level was also developed in this thesis. Furthermore, a baseline simulation flow was established to compare our approach to those converters available in the literatures. It demonstrates the advantages of our approach in various performance measures even though we are using a more matured technology.

摘要    I
Abstract    II
致謝    III
Table of contents    IV
Lists of Figures    VIII
Lists of Tables    XIV
Chapter 1 Introduction    1
1. Motivation    1
2. Background of DPWM    3
3. Related works and Proposal    4
4. Organization of the thesis    5
Chapter 2 Background of DPWM DC-DC buck converter    7
1. Introduction of DC-DC buck converter    7
1.1. Architectures of DC-DC buck converter    8
1.2. Switching modes of DC-DC buck converter    11
1.3. Current control modes of DC-DC buck converter    13
2. Introduction of pulse width modulation    15
2.1. Principle of pulse width modulation    15
2.2. Analog pulse width modulation (APWM)    16
2.3. Digital pulse width modulation (DPWM)    18
3. Chapter summary    19
Chapter 3 Architecture of DPWM DC-DC buck converter    21
1. Output stage    22
2. Sample-and-hold circuit    25
3. Analog to digital converter (ADC)    26
3.1. Counter ADC    27
3.2. Flash ADC    28
3.3. Pipeline ADC    29
3.4. SAR ADC    30
4. Digital compensator circuit    33
4.1. Digital PID controller    33
4.2. Tuning method for PID compensator    35
5. Digital pulse width modulation (DPWM)    36
5.1. Delay-line DPWM generator    37
5.2. Counter-based DPWM generator    38
6. Chapter summary    40
Chapter 4 Implementation approaches    41
1. Dither method    42
1.1. Dither patterns    44
1.2. Dither ripple estimate    45
1.3. Dither generator scheme    46
2. Negative dither method    47
2.1. Harmonic effects by Negative dither method    48
2.2. Negative dither generator scheme    48
3. RC method    50
3.1. Operation principle and scheme    51
3.2. Resolution estimation    52
4. Proposed integrated method    55
4.1. Concept and principle    56
4.2. Scheme of proposed integrated method    58
5. Chapter summary    59
Chapter 5 Implementation and simulation results    60
1. Conventional DPWM DC-DC buck converter    61
1.1. Output stages    62
1.2. Analog to digital converter (ADC)    65
1.3. Digital PID controller    69
1.4. Digital pulse width modulation (DPWM)    73
1.5. Simulation results    76
2. DPWM DC-DC buck converter with novel methods    78
2.1. Dither method    78
2.2. Negative dither method    83
2.3. RC method    86
2.4. Proposed integrated method    89
2.5. Performance tolerance of Proposed integrated method    95
3. Chapter summary    99
Chapter 6 Conclusion and future work    100
1. Conclusion    100
2. Future work    103
Reference    104


                                

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