為了滿足ITRS元件持續縮小化的要求，一般廣泛的認為高介電係數材料將取代原本的二氧化矽成為金氧半元件閘極介電層來改善漏電流的問題，然而在材料替換的過程中，許多問題產生，如電荷捕獲(charge trapping)，臨界電壓(threshold voltage)飄移，載子遷移率(mobility)下降等，因此應用在高介電係數閘極介電層電晶體的界面陷阱(interface traps)及氧化層陷阱(oxide traps)可靠度分析因應而生。
論文中第一部份介紹電荷汲引技術量測方法。藉由改變電荷汲引量測技術中輸入之閘極脈衝波上升/下降時間，可以計算界面陷阱在矽能隙中能量分佈。利用不同脈衝波操作頻率，我們可以得到在high-k介電層電晶體邊緣陷阱的分佈。結合上述兩者，我們可以進一步得到邊緣陷阱的能量分佈情況。
論文最主要探討不同stress對high-k介電層產生的影響。結合電荷汲引量測技術量測經過stress之後high-k介電層電晶體界面陷阱與邊緣陷阱的變化。觀察到F-N stress造成邊緣陷阱的產生，CHC stress造成界面陷阱的產生。最後探討高溫時stress對元件的影響，期望對元件使用年限與陷阱產生及分佈的關係有進一部的了解。

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