使用穿矽孔(TSV)的三維晶片(3D IC)技術被廣認為是未來積體電路發展的趨勢之一。穿矽連接孔主要可能遭受到兩種參數性的錯誤影響－電阻性開路錯誤或漏電流錯誤。不同於針對定值錯誤(stuck-at faults)，這些參數性錯誤並不會完全破壞穿矽孔的傳輸功能，但是會對穿矽連接孔的效能與品質造成影響。

根據之前的研究，我們提出的可變輸出閥值(Variable Output Threshold)的方法能有效的掌握穿矽連接孔延遲錯誤。以此為基礎，我們提出一個用於接合後(post-bond)的穿矽孔且能近距離同時掌握兩種參數性錯誤的完善評估三維晶片鍵合後穿矽孔的特性之流程。藉由此流程，使用者能更貼切的掌握到參數性的錯誤，可應用於生產性試驗、製程監控和良率分析上的錯誤診斷。在測試時脈為10MHz，可調整式的測試介面在1024個穿矽孔的情況下需要17.2ms的測試時間，而在32,768個穿矽孔的情況下需要648.8ms的測試時間。

Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A TSV could suffer from two major types of parametric faults – a resistive open fault, or a leakage fault. Unlikely to stuck-at faults, these parametric faults do not destroy the functionality of a TSV completely but degrade its quality or performance. Based on our previous test structure, called VOT (Variable Output Threshold) scheme for delay faults, we propose a unified in-situ characterization flow for both parametric fault types of a post-bond TSV. With this flow, one can easily derive a more insightful assessment of a parametric fault in production test, process monitoring, and diagnosis-driven yield learning. A scalable test infrastructure indicates that the test time is modest at only 17.2 ms for 1024 TSVs and 648.8 ms for 32,768 TSVs when the test clock is running at 10MHz.

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