研究生: |
吳冠穎 |
---|---|
論文名稱: |
影響生產良率之WAT參數與機台解析模式 A yield Analysis Model for Correlating Critical WAT Parameters with Machines |
指導教授: | 陳飛龍 |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 工業工程與工程管理學系 Department of Industrial Engineering and Engineering Management |
論文出版年: | 2006 |
畢業學年度: | 94 |
語文別: | 英文 |
論文頁數: | 79 |
中文關鍵詞: | 半導體 、良率 、WAT 、決策樹 、逐步分析法 |
外文關鍵詞: | Semiconductor, Yield, WAT parameter, Decision tree, Stepwise regression |
相關次數: | 點閱:1 下載:0 |
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良率是個很重要的議題在半導體產業中。在半導體體製程完成後,晶圓允收測試(WAT)能夠測試出晶圓製造的成果。因此,我們相信在WAT測量值與良率之間存在著某種關係。傳統半導體產業,當發現低良率的情況時,診斷工程師需要從大量且複雜的工程資料中來判定低良率的根本原因。除此之外,工程師還需要跟各部門的人員一同討論來找原因。這種行為是非常浪費時間和人力資源的。本研究打算發展一方法論能夠有效減少需要處理的工程資料量以用來幫助工程師快速且有效的判定低良率的原因,而且不需要專業知識的協助。本方法論是打算利用WAT參數來判定低良率的原因(製造過程的某機台)。此方法論的目標是要揭露低良率的現象與某些WAT參數的關係以及建立這些WAT參數和某些關鍵機台的相關係數表。透過相關係數表可以幫助工程師快速判定低良率的原因。本研究使用決策樹中自動卡方檢驗法(CHAID)演算法來尋找WAT參數與低良率的關係,在WAT參數與關鍵機台這部份是使用逐步分析與相關分析法。最後,取得真實半導體產業的資料套入方法論中來衡量此方法論的成效。
Wafer yield is the most important issue in the semiconductor industry. Wafer Acceptance Test (WAT) diagnoses performance of wafers after the manufacturing process has been completed. Therefore there exists relationship between the WAT measurements and wafer yield. Traditionally, engineers determine the root causes (critical machines) of low wafer yield via a lot of complicated engineering data as a low yield problem occurs. In addition, diagnosis engineers have to communicate with other engineers to explore the root causes. The task takes a lot of time and human resources. Thus this research attempts to develop the methodology to help engineers to efficiently detect the root causes of low wafer yield by decreasing the volume of engineering data. This methodology can be used to automatically find out the root causes of low yield via WAT parameters. Therefore, the aim of this research is to explore the relationship between low yield and WAT parameters and to establish a mapping table to reveal the relationship between WAT parameters and critical machines. The mapping table can help engineers to determine the root causes more efficiently. To be specifically, the relationship between low yield and WAT parameters is explored by using the decision tree (CHAID) algorithm. The relationship between WAT parameters and critical machines is derived via the stepwise regression model and correlation analysis. Finally, engineering data from a real-world semiconductor manufacturer are employed to evaluate the performance of the proposed methodology.
簡禎富,林鼎浩,彭誠湧,徐紹鐘,建構半導體晶圓允收測試資料挖礦架構及實證研究,工業工程學報,第18卷,第四期,pp.37-48,2001年
李偉傑,半導體之工程資料分析與診斷系統,國立清華大學工業工程研究所未出版碩士論文,民國86年
盧文彬,半導體晶圓允收測試之工程資料分析與診斷研究,國立清華大學工業工程研究所碩士論文,1997年
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