這篇論文提出一種用於穿矽連接孔的各階段測試方法，而這各階段測試方法其中包括堆疊前、堆疊中和堆疊後測試。推疊前的測試是要用來確認各個裸晶在堆疊前是否都是ㄧ個正常的裸晶，如此來增加最終的良率。堆疊中的測試則是要確保每一次的堆疊是否都有成功的堆疊，如果在堆疊中發現堆疊錯誤則不必繼續的往下堆疊。堆疊後的測試則是用來確認最終的堆疊是否有成功，如此複雜測試過程是目前對於3D IC的完整流程，但是目前比較少可以有一個簡單的方法可以完整的用於3D IC的測試流程，而我們的測試方法可以達到。
我們重複使用一樣的測試電路來達成我們的測試方法。在我們使用的測試結構中，我們將所有的測試單元以一個連一個的方式串接成全局震盪環，且使用daisy chain和TAP控制器來輔助我們的測試方法。藉由此方法我們可以簡化先前局部環的測試方法中遇到的測試結果檢索問題。雖然我們的方法無法在堆疊前的階段達到百分之百穿矽連接孔的故障位置覆蓋率，但是我們可以在堆疊後的階段做到。
而我們的測試方法會針對3D IC中的穿矽連接孔進行各種的參數性故障進行測試，分別是在穿矽連接孔中可能會造成額外延遲的open fault，我們會針對open fault所造成的大電阻和故障位置來分析，還有在穿矽連接孔中的leakage fault，同樣我們會針對leakage fault所造成的大電導和故障位置分析，最後則是會連接穿矽連接孔兩端的bridging fault，我們會針對bridging fault中連接兩端的電阻來分析。

This thesis presents an any-bond test method for TSV, and any-bond test means that including pre-bond, mid-bond, and post-bond test. We repeatedly use the same set of design-for-testability circuits to achieve our test method. In our test architecture, all the test wrappers are cascaded one after another to form a global ring oscillator, and we use daisy-chain and test access protocol controller to support our test method. By doing so, the test-result retrieval problem in previous local-ring based method can be alleviated. Even though our method can’t achieve the 100% fault location coverage for overall TSV in the pre-bond stage, we can do that in post-bond stage.

[1] K. Chakrabarty, “TSV Defects and TSV-Induced Circuit Failures: The Third Dimension in Test and Design-for-Test”, Proc. of Int’l Reliability Physics Symp., (IRPS), pp. 5F1.1-5F.1.12, 2012.
[2] H. Lee and K. Chakrabarty, “Test Challenges for 3-D Integrated Circuits,” IEEE Design and Test of Computers, Vol. 25, No. 5, pp. 26-35, Sept.-Oct. 2009.
[3] L.-R. Huang, S.-Y. Huang, K.-H. Tsai, and W.-T. Cheng, “Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs”, IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD), Vol. 33, No. 3, pp. 476-488, March 2014.
[4] E. J. Marinissen, “Challenges and Emerging Solutions in Testing TSV-Based 2.5-D and 3D-Stacked ICs,” Proc. of IEEE Design, Automation, and Test in Europe Conf., pp. 1277-1282, 2012.
[5] D. Arumí, R. Rodríguez-Montañés, J. Figueras, “BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing,” Proc. of European Test Symp., 2013.
[6] P. Y. Chen, C. W. Wu, and D. M. Kwai, “On-Chip TSV Testing for 3D-IC Before Bonding Using Sense Amplification,” Proc. of IEEE Asian Test Symposium, pp. 450-455, Nov. 2009.
[7] P. Y. Chen, C. W. Wu, D. M. Kwai, “On-Chip Testing of Blind and Open-Sleeve TSVs for 3D IC before Bonding,” Proc. of IEEE VLSI Test Symp., pp. 263-268, April 2010.
[8] M. Cho, C. Liu, D. H. Kim, S. K. Lim, and S. Mukhopadhyay, “Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System,”IEEE Trans. on Components Packaging and Manufacturing Technology, Vol. 1, No. 11, Nov. 2011..
[9] S. Deutsch and K. Chakrabarty, “Non-Invasive Pre-Bond TSV Test Using Ring Oscillator and Multiple Voltage Levels,” Proc. of IEEE Design Automation and Test in Europe, pp. 1065-1070, March 2013.
[10] L.-R. Huang, S.-Y. Huang, S. Sunter, K.-H. Tsai, and W.-T. Cheng "Oscillation-Based Pre-Bond TSV Test," IEEE Trans. on Computer-Aided Design of Electronic Circuits, Vol. 32, No. 9, pp. 1440-1444, Sept. 2013.
[11] B. Noia and K. Chakrabarty, “Pre-bond probing of TSVs in 3D Stacked ICs,”Proc. of Int’l Test Conf., pp. 1-10, 2011.
[12] M. Tsai, M. Klooz, A. Leonard, J. Appel, and P. Franzon, “Through Silicon Via (TSV) Defect/Pinhole Self Test Circuit for 3D-IC,”Proc. of Int’l Conf. on 3D System Integration, pp. 28-30, Sept. 2009.
[13] C.-C. Chi, C.-We. Wu, M.-J. Wang, H.-C. Lin, “3D-IC Interconnect Test, Diagnosis, and Repair,” Proc. of IEEE VLSI Test Symp, pp. 1-6, 2013.
[14] S.-Y. Huang, J.-Y. Lee, K.-H. (Hans) Tsai, and W.-T. Cheng, "Pulse-Vanishing Test for Interposers Wires in 2.5-D IC", IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD), (accepted to appear).
[15] Y. J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A Built-In Self-Test Scheme for the Post-Bond Test of TSVs in 3D ICs,” Proc. of IEEE VLSI Test Symp, pp. 20-25, 2011.
[16] K. S.-M. Li, C. L. Lee, C. Su, and J. E. Chen, “Oscillation Ring Based Interconnect Test Scheme for SoC,” Proc. of IEEE Asia South Pacific Design Automation Conf. (ASP-DAC), pp. 184–187, 2005.
[17] Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F. Chou, and D.-M. Kwai, “Small Delay Testing for TSVs in 3D ICs,” IEEE Proc. of Design Automation Conf., June 2012.
[18] R. Wang, K. Chakrabarty, and B. Eklow, “Post-Bond Testing of the Silicon Interposer and Micro-Bumps in 2.5D ICs,” Proc. of IEEE Asian Test Symp., pp. 147-152, 2013.
[19] F. Ye and K. Chakrabarty, “TSV Open Defects in 3D Integrated Circuits: Characterization, Test, and Optimal Spare Allocation”, Proc. of Design Automation Conf., pp. 10240-1030, June 2012
[20] J.-W. You, S.-Y. Huang, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, "Performance Characterization of TSV in 3D IC via Sensitivity Analysis," Proc. of Asian Test Symposium (ATS), Dec. 2010.
[21] E. J. Marinissen, C.-C. Chi, J. Verbree, and M. Konijnenburg, “3D DfT Architecture for Pre-Bond and Post-Bond Testing,” Proc. of 3D Systems Integration Conf., pp. 1-8, 2010
[22] P. R. O’Brien and T. L. Savarino, “Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation,” Proc. of Design Automation Conf., pp. 512–515, Nov. 1989
[23] S. H. Wu, D. Drmanac, L.-C. Wang, “A Study of Outlier Analysis Techniques for Delay Testing,” Proc. of IEEE Int’l Test Conf., pp. 1-10., 2008
[24] IEEE Computer Society, “IEEE Std 1149.1TM-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE, June, 2001
[25] “CIC Reference Flow for Cell-based IC Design”, Chip Implementation Center, CIC, Taiwan, Document no. CIC-DSD-RD-08-01, 2008