本論文探討了幾個射頻前端的設計技術，如何以最大的功率效益來達到最佳的電路效能轉換。本論文可區分為兩大主軸，第一是在寬頻低雜訊放大器的電源效能轉換上的設計抉擇，特別是在雜訊壓制的考量上。畢竟手持式裝置有限使用時間的電池限制，低耗功的電路一直為設計者所感到有趣且挑戰的事。另一主軸為寬頻系統中，諧波抑制的干擾等問題。傳統常為了解決此一問題，所付出的大量功耗與製作成本。如何降低這樣的影響，便是此論文的重點所在。
對於高功率效益寬頻放大器的設計，分為兩個主題。第一為有電感使用的放大器，另一種為無電感放大器。在有電感使用的放大器中，我們提出了利用被動的匹配網路來形成阻抗的轉換，重新分配能量的變化，進而達到訊號電壓的放大，此類匹配網路雖然能提供的增益有限，亦大多受限於製程的條件，但其高線性度與無功耗的優點，是非常適合於寬頻系統或是近距離通訊的接收前端裝置。此論文實現並驗證的寬頻與窄頻網路設計與量測，可供於傳統電路作為參考。在無電感使用的放大器電路上，本論文提出訊號無效的雜訊抑制回授電路。此技術相較於傳統更能有效的利用功耗來達成雜訊的抑制。
在寬頻系統中，傳統切換式的降頻器為了解決諧波混頻的抑制，不僅花費了極大的功率損耗以及製作成本，更對於接收的射頻訊號造成品質的下降。本論文提出了一個新穎的電路架構將一個原本為系統性的問題，轉換成電路上的設計技巧。此方法稱之為B類線性降頻器。不僅降低了系統架構的複雜度，也因為順利的解決諧波混頻干擾，無須額外的電路功率消耗，所以使得整個寬頻接收器架構與傳統窄頻相似，達到低成本、低耗功的目標。另外延伸此一方法，亦設計了一組射頻前端接收機並搭配傳統多相位降頻法來達到更高的諧波抑制，讓整個接收機能有更加確保的諧波抑制功能，以符合現今最流行的數位電視接收機等應用。

This thesis investigates several RF front-end design techniques to maximize the power efficiency
for performance tradeoffs in wideband applications. There are two major aspects. One
is the design tradeoff between the power consumption and signal quality, especially on noise
performance in wideband low-noise amplifiers (LNA), since the challenge of limited battery
life-time in portable device makes the power-efficiency always a topic of interest. The other
is the harmonic mixing problem in frequency conversion of wideband systems. The problem
causes larger penalties of power and cost when it has to be concerned.
For the power-efficient LNA design, a series of passive techniques without power supplies
are introduced for some non-stringent wireless applications. The impedance transformation is
used to provide a voltage gain for reducing the power budget in an RF chain. Both narrowband
and wideband amplifiers are realized to demonstrate the passive performance. Moreover, a
voltage-mode passive mixer is introduced for a case study of fully passive RF front-end. A
straight-forward derivation of the conversion gain is introduced to describe the physical meaning
of the conversion.
For another case of inductor-less wideband LNAs, due to the lack of the finesse from the
matching network, the design tradeoffs are more rigid in many circuit topologies, especially
on trading for noise performance. In this thesis, a noise suppression feedback technique is
proposed to alleviate the power requirement on noise reduction. The technique has been successfully
applied to an RF LNA and a baseband variable-gain amplifier to demonstrate the feasibility
of the noise suppression. The results break the fundamental power overhead for noise
improvement. This technique is also integrated in a noise-suppressed, linearity-enhanced, and
bandwidth-extended LNA with high power efficiency.
The second part of the thesis is to resolve the harmonic mixing problem without heavy
power and cost penalties. In this thesis we develop a new mixer structure named class-B-like
linear conversion. The conversion exhibits noise performance near a switching-type one, while
its harmonic mixing rejection is comparable with the conventional rejection techniques. The
class-B-like mixer consumes 4.8 mW from a 1.8V supply voltage. The chip area is only 270m
x 190m. Measurement results indicate that the third- to ninth-order harmonic rejections are
more than 45 dB in average within 4-GHz frequency range.
To further extend the usage of the class-B-like operation, a digital TV RF front-end integrates
the technique associated with a conventional polyphase harmonic cancellation. This
prototype contains an LNA, a polyphase down-conversion with the class-B-like mixing, and a
square-to-triangle waveform generator for the compatibility to digital-output frequency synthesizers.
From measurement results, although the low frequency performance is limited by the
waveform generator, this idea can still be proven as a high power efficient solution for harmonic
mixing rejection in a wideband receiver design.

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