在目前記憶體階層中，儲存裝置以快閃記憶體為主，不過因其低存取速度及低耐久性，使之與主記憶體之動態存取記憶體存在效能落差，將會造成記憶體系統之效能瓶頸。新興之記憶體概念”儲存級記憶體(SCM)”作為儲存裝置及主記憶體間溝通之橋梁，一些新興的非揮發式記憶體(例如: 電阻式記憶體、磁阻式記憶體)因其低操作電壓與優異的表現，已經成為取代快閃記憶體且應用於儲存級記憶體之最佳可能選擇。在眾多新興非揮發式記憶體中，自旋力矩轉移-磁阻式隨機存取記憶體因其高速存取、高耐久性與非揮發的特性，將在此新領域中扮演重要之角色。然而自旋力矩轉移-磁阻式隨機存取記憶體在讀取上會將面臨以下之挑戰，:
1. 自旋力矩轉移-磁阻式隨機存取記憶體之穿隧式磁阻比例(TMR-Ratio)小的特性及製程飄移現象，造成資料0與資料1之阻值差異性小，導致讀取良率低落。
2. 自旋力矩轉移-磁阻式隨機存取記憶體之元件阻值偏低，造成在長位元線的情況下，資料0與資料1的阻值差異會被位元線的寄生電阻稀釋，造成讀取良率低落。
此外，在新一波人工智慧的浪潮下，隨著深度學習網路的發展，內嵌式記憶體系統之帶寬需求不斷增加。隨著在記憶體巨集(macro)內置入更多的讀取電路，高功耗與高峰值電流帶來的問題需要被正視。
在此次碩士論文中將探討當需要在自旋力矩轉移-磁阻式隨機存取記憶體巨集中實現高帶寬的需求時會遇到的挑戰以及新提出的讀取架構是如何應對這些問題。我們提出的讀取架構包含兩個部分，分別是
1. 自適應局域參考電流產生機制
2. 兩比特電流感測放大器
此架構具備了電流域度放大、製程變異容忍、低峰值電流與低能耗的特性來解決前述困境。
在台積電22奈米製程模擬分析下，我們提出的讀取架構的相較於傳統電流感測放大器可容忍3倍至7.5倍以下之可讀取TMR-比例，並相對傳統電流讀取在位元線長度為512個記憶胞(memory cell)與1024個記憶胞減少48%及53%的能量消耗。在峰值電流方面，新的讀取架構相對於傳統電流讀取架構可以減少58%與59%之峰值電流。此外，在特別為深度學習網路設計的巨集讀取模式下，相對於傳統架構可以節省58%的能耗。
我們與台積電合作並以22奈米與55奈米製程實作2Mb/0.5Mb STT-MRAM/ReRAM記憶體晶片且本篇的量測結論暫時以55奈米為主。在正常操作電壓1V下，當位元線長度為512記憶胞，量測提出之電路讀取速度為6.5奈秒(ns)。

In current memory system hierarchy. The performance gap is occurring between main memory (DRAM) and storage (flash memory) due to slow access speed and low endurance of flash memory. The performance gap will cause memory system performance bottleneck. A new memory concept, storage class memory (SCM) is proposed, which act as the bridge between storage memory and main memory. Emerging non-volatile memories (i.e. ReRAM or MRAM) require lower operating voltage with better performance than Flash memory and aim to replace flash memory in SCM. Among all of the emerging non-volatile memories, Spin Torque Transfer-Magnetoresistive Random Access Memory (STT-MRAM) is a promising candidate for its high speed accesses, high endurance and non-volatility. However, STT-MRAM faces some challenges:
1. The low TMR-ratio of STT-MRAM cell and process variation effect, resulting in small resistance difference between data-0 and data-1. Therefore, leading to low sensing yield.
2. The low resistance value of STT-MRAM cell makes it vulnerable to the high parasitic resistance on long BL length, which resulting in low sensing yield.
In addition, in the next A.I. era, deep neural network (DNN) plays a role and requires the high throughput in embedded memory system. With more sensing amplifiers is implemented in one macro, the large energy consumption and high peak current issue should be handled.
In this work, we discuss the issue in high bandwidth reading especially with STT-MRAM, and proposed a read scheme includes:
1. Adaptive- Local Reference current generating scheme (AL-REF)
2. 2-bit Current Mode Sense Amplifier (2B-CSA)
which is featured with margin enhancement, offset suppression, low peak current, and low energy consumption capability to solve the problems mentioned before in STT-MRAM high bandwidth macro.
Under tsmc 22 nm technology analysis, our proposed work achieves >3x~7.5x lower tolerance on TMR ratio at a given R¬P than conventional scheme. Moreover, it can achieve 48% and 53% lower read energy than conventional SA under the BL length equals 512/1024 cells. The peak current is reduced by 58% and 59% compared to conventional SA under the BL length of 512/1024 cells. In addition, the macro energy consumption is improved by 58% with the specially designed operation mode for DNN.
Finally, our proposed scheme is verified in both a 0.5Mb ReRAM macro fabricated in TSMC 55nm CMOS process and a 2Mb STT-MRAM macro fabricated in TSMC 22nm CMOS process, and the measurement result is temporarily depending on 0.5Mb macro. The measured access time of proposed work is 6.5ns at typical VDD = 1V and BL-length = 512.

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