低功率設計已成近年來超大型積體電路設計重要的研究議題，隨著晶片製成技術高速的進展，單位面積所能容納的半導體數目每十八個月即增加一倍，因此，單位面積所造成的功率消耗也大幅增加。此外，隨著可攜式裝置的日漸普及，手機、筆記型電腦、個人數位助理(PDA)，它們具備了相同的特性─無法長時間有固定的電源供應，因此，低功率的設計將使得這些可攜式裝置能有更長的使用時間。
在本篇論文中，我們從探討二元決策圖的特性以及在PTL上的應用出發，接下來，我們展現一些合成低功率PTL的方法。PTL單元的功率消耗可以分成電流流經柵極和源極/射極的電容所造成的結果。藉由新的功率消耗模型，我們希望能進一步地得到低功率的電路設計方法。

我們把尋找一個低功率PTL的問題轉化成為尋找一個伴隨較低成本消耗的二元決策圖。這個成本消耗應該考量把高變化率的變數出現的機會較少，以及減小二元決策樹的期望路徑長度。由過去的經驗得知，兩者所佔的比重接近一比一。為了有效率的計算成本消耗，我們提出了三個有效率的方法以輔助計算二元決策圖的期望路徑長度。

實驗結果顯示，我們所提出的方法將比傳統的方法更能達到低功率的電路設計。此外，在效能上，我們提出較快速的演算法也將進一步地提昇因為計算所造成的延遲。

In this paper, we present methods to synthesize low power Pass Transistor Logic (PTL) cell. Given that the power consumption of a PTL cell includes power consumed at the gate terminal and source/drain capacitance when current flows from power/ground to output, we will translate finding a low power PTL cell to finding an OBDD with some defined cost function. This cost function includes the minimization of occurrence of variables with high transition probability and the minimization of the expected path length of an OBDD. To compute the cost function efficiently, three methods will be proposed to calculate the expected path length of Ordered Binary Decision Diagrams (OBDD).

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