延遲變動可能會造成電路沒有辦法符合它的時序要求。Razor[5,12]這個研究觀察到電路裡的最壞情況很難會發生。他們提出了一個機制能夠偵測並更正那些不常發生的錯誤，因此電路可以對一般的情況最佳化。他們的實驗結果顯示出它的系統跟那些專為最壞情況最佳化的設計比起來，在效能及耗能上都有極大的增進。雖然如此，他們的系統有著在先進製程上有著難以解決的短路徑問題。在這篇論文裡，我們提出一個時序錯誤偵測系統，由於不需要用一個延遲時脈，所以這個系統並不會有短路徑問題。給定一個原有電路跟一個最大的延遲限度，我們的演算法能夠自動的建造出一個能夠容忍給定的延遲限度的系統。我們的實驗結果顯示出這個系統，在那些最小延遲限制難以達成的設計中，可以當作Razor 的一個良好替代系統。

Delay variation can cause a design to fail its timing specification. Research [5, 12] observes that the worst case of a design is highly improbable to occur. They propose a mechanism to detect and correct occasional errors while the design can be optimized for the common cases. Their xperimental results show significant performance or power gain as compared to the worst-case design. However, the architecture in [5, 12] suffers the short path problem which is difficult to resolve in the advanced technology. In this thesis, we propose a Timing Error Detection (TED) architecture without using a delayed clock and therefore the TED architecture is free from the short path problem. Given a design and a maximum delay margin, our algorithm
can automatically construct a TED architecture to tolerate the given delay margin. Our experimental results also show that the TED architecture can be a good alternative for those cases where the minimum delay is difficult to
meet in the advanced technology.

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