后羿(Hypothesis, Odyssey, and Yield, HOY)計畫提出一個新的IC測試技術，經由無線射頻傳輸通道來傳輸資料，藉此來取代傳統測試機台ATE之探針卡。儘管后羿系統的目標是減少測試上的成本，
但是無線射頻傳輸通道其易受干擾的特性也會影響到其測試過程。在做封裝(Production)之前，為了利用后羿模組來取得電路的電性特性(Characterize effect)，我們提出了一個新的方法，即在待測電路上(Device Under Test, DUT)額外置入有線測試介面。此新的介面適用於IEEE 1149.1 JTAG的標準，其介面可經由較小的人力來整合進封裝測試(package test)裡。而其有線測試介面之模組則是參考OpenCores計畫所提供的JTAG模組電路，與另一傳輸模組ADI，使其后羿的待測電路能經由JTAG來與軟體端溝通。而軟體端也參考OpenCores所提供的硬體driver使其能讓后羿的測試程式與硬體driver結合，進而能與硬體端銜接。除此之外，我們亦提供GUI介面，使其在操作上更加容易。由於其JTAG的架構相較於后羿系統簡單，故其所加入的介面面積僅占5.8K邏輯閘。其測試介面功能已藉由RTL模擬與FPGA平台驗證過。此外，對於電性測試(Characterizing test)，我們可經由此介面來使其在使用上與原本的后羿模組互補。譬如，做Wafer sort時，我們可以利用后羿的無線測試，做封裝測試時則可以利用有線測試介面，最後做測試與診斷功能時，可經由后羿的無線傳輸通道來實現。

The HOY project proposed a new methodology of IC test to use RF wireless channels to transfer
data instead of probe cards in traditional ATE. Even though the goal of a HOY system is to
reduce the test cost, it also introduces the unreliability factors of RF communication into the tests.
In order to characterize effects by HOY modules before production, we propose to add an additional
wired interface to DUTs. The new interface is compatible to IEEE 1149.1 JTAG, which
reduces the effort to integrate with package tests. Because of the relatively simple architecture
of a HOY system and JTAG, the added interface consume only 5.8K gates (in addition to HOY
modules). Both RTL simulation and FPGA prototype are used to verify the new interface. Besides
the role of characterizing tests for HOY, we can also use the interface to complement the usage
of HOY modules. For example, HOY wireless tests can be used in wafer sorts, while the wired
interface can then be utilized in packaged tests, and finally wireless channel can be used again in
field test/diagnosis.
1

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