時鐘網路對超大型積體電路的效能和特性有很大的影響。因為有
很大部份的功率消耗在時鐘網路上，所以時鐘網路的低功率課題變成
重要的研究領域。在循序電路中，時鐘閘控制是一種很有效率的低功
率設計方法。在我們的方法中，我們提出了一種快速的拓樸排序建構
法，並且配合零時差閘控制時鐘網路建構。我們在建構拓樸排序時就
考慮了物理位置，輸入電容，動作型態。因此我們的方法可以建構出
適合閘控制時鐘網路繞線的拓樸。實驗結果證明我們的方法比起之前
的方法，可以改善大約４％－１０％功率

Clock networks aect the performance and property of VLSI circuits greatly. Power reduction
issue for the clock network becomes an active research area since a large portion of
power is dissipated on clock networks. Clock gating is an eective power reduction technique
in sequential circuits. In this work, we propose a fast topology generation algorithm
that feeds to zero-skew gated clock network construction. It considers the physical locations,
input capacitances, and activity patterns of clock sinks in topology generation stage.
Therefore, our algorithm generates an appropriate topology for gated clock routing engine.
we also extend the buered/gated models in our works. The experiment results show that
our approach gains 4%-10% improvements on power saving against previous works.

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