研究生: |
洪子欽 Hong, Zi-Qin |
---|---|
論文名稱: |
高介電閘場效電晶體之可靠度與輻射效應研究 Reliability and Radiation Effects in High-k Gated FET |
指導教授: |
連振炘
Lien, Chen-Hsin 張廖貴術 ChangLiao, Kuei-Shu |
口試委員: |
趙天生
Chao, Tien-Sheng 劉柏村 Liu, Po-Tsun |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2020 |
畢業學年度: | 109 |
語文別: | 中文 |
論文頁數: | 138 |
中文關鍵詞: | 鍺電晶體 、輻射傷害 、可靠度 、負偏壓溫度不穩定性 |
外文關鍵詞: | Ge MOSFET, Radiation Damage, Reliability, NBTI |
相關次數: | 點閱:1 下載:0 |
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可靠度與輻射效應對積體電路(IC)元件是很重要的研究課題。因為在IC元件製造中的電漿製程及EUV微影技術,或是元件應用於航太科技、或衛星通訊都可能處在高能輻射的環境中。高介電係數材料(high-k)閘極已為先進IC元件所使用,因此閘介層的可靠度與輻射傷害值得探討研究。
本論文第一部份,透過不同通道結構來改善電晶體電特性,可以克服短通道效應所造成的問題。對平面式、鰭式以及全環繞式電晶體,經不同輻射傷害後,對元件之電性與可靠度分析。由電晶體電特性的比較,全環繞式電晶體相較於平面式電晶體與鰭式電晶體,有較佳的抗輻射能力。
為了將摩爾定律進一步擴展到5nm以下的技術節點,將鍺材料用於取代矽被視為一種前瞻的解決方案。其不僅擁有比矽更高的載子遷移律,製程技術更與傳統矽製程相容。然而,鍺電晶體的界面品質較差將是其發展的瓶頸。本論文第二部份,探討金屬閘極與high-K閘介電層之界面製程對鍺電晶體電性之影響。High-K氧化層與金屬閘之間以原子層沉積(ALD)成長TiN,來減少界面缺陷、抑制漏電流,可以獲得較佳的元件及抗輻射特性。
第三部份,應用超臨界流體處理來鈍化原子層沉積的閘極介電層,通過SC CO2將H2O分子帶入氧化物薄膜中,並且添加乙醇來增強反應。SC CO2+H2O+乙醇的處理可減少閘極介電層中的缺陷,提升電晶體之電特性。
最後,透過電荷汲引技術(Charge Pumping technique),探討超臨界流體製程處理的鍺電晶體在經NBTI stress及輻射照射後,對於界面態陷阱(Nit, interface trap)與氧化層陷阱(Not, oxide traps)之影響。因SC CO2+H2O+乙醇的處理可以減少閘極介電層中的缺陷,使元件經輻射照射後有較少的界面陷阱產生,可以獲得較佳的元件及抗輻射特性。
Reliability and radiation effects are very important research topics for integrated circuit (IC) devices, because the IC devices may be in a high-energy radiation environment when a plasma process or EUV lithography are used in IC production, or IC devices are applied in aerospace or satellite communications. Since high-k gate dielectrics are widely implemented in modern IC, the reliability and radiation damage on them are worthy of study.
In the first part of this thesis, the short channel effects of field effect transistor (FET) are reduced and electrical characteristics can be improved by modifying channel structure. The effects of radiation damages on electrical characteristics and reliability of MOSFET, FinFET, and GAAFET were studied. Based on the comparison of electrical characteristics, GAAFET shows better radiation hardness than FinFET and planar MOSFET.
In order to further extend Moore’s law beyond sub-5nm node, Ge is regarded as a promising channel material to replace Si because of not only its much higher carrier mobility but also the compatibility with Si manufacturing technology. However, the poor interface quality of Ge MOSFET is the bottleneck for its development. In the second part of this thesis, the process integration of metal gate/high-k gate dielectric for improving radiation hardness of Ge MOSFET was investigated. The electrical characteristics and radiation hardness of Ge MOSFET can be clearly improved by using an atomic layer deposition (ALD)-formed TiN between high-k gate dielectric and metal gate to decrease the border trap and reduce the leakage.
In the third part of this thesis, a supercritical fluid (SCF) treatment was applied to passivate the ALD formed-gate oxide. The H2O molecules are carried into the oxide film by SC CO2, and the reaction can be enhanced by adding ethanol. The defects in gate dielectric can be reduced and the electrical characteristics of Ge MOSFET can be clearly improved by a SC CO2+H2O+ethanol treatment.
Finally, a charge pumping technique was used to assess the negative bias temperature instability stress and radiation exposure induced oxide and interface traps in Ge MOSFET with SCF treatment. The electrical characteristics and radiation hardness of Ge MOSFET can be clearly improved by a SCF treatment with SC CO2+H2O+ethanol, because the defects in gate dielectric may be reduced.
[1] S. Takagi et al., "III–V/Ge channel MOS device technologies in nano CMOS era," Japanese Journal of Applied Physics, vol. 54, no. 6S1, 2015.
[2] K. Prabhakaran, F. Maeda, Y. Watanabe, and T. Ogino, "Thermal decomposition pathway of Ge and Si oxides: observation of a distinct difference," Thin Solid Films, vol. 369, pp.289-292, 2000.
[3] K. Kita, C. H. Lee, T. Tabata, T. Nishimura, K. Nagashio, and A. Toriumi, "Desorption kinetics of GeO from GeO2/Ge structure," Journal of Applied Physics, vol. 108, no. 5, 2010.
[4] D. Kuzum, P. Jin-Hong, T. Krishnamohan, H. S. P. Wong, and K. C. Saraswat, "The Effect of Donor/Acceptor Nature of Interface Traps on Ge MOSFET Characteristics," IEEE Transactions on Electron Devices, vol. 58, no. 4, pp.1015-1022, 2011.
[5] G. Lucovsky, S. Lee, J. P. Long, H. Seo, and J. Lüning, "Elimination of GeO2 and Ge3N4 interfacial transition regions and defects at n-type Ge interfaces: A pathway for formation of n-MOS devices on Ge substrates," Applied Surface Science, vol. 254, no. 23, pp.7933-7937, 2008.
[6] D. Kuzum et al., "High-Mobility Ge n-MOSFETs and Mobility Degradation Mecha-nisms," IEEE Transactions on Electron Devices, vol. 58, no. 1, pp.59-66, 2011.
[7] C.-W. Chen et al., "Enhancing the Performance of Germanium Channel nMOSFET Using Phosphorus Dopant Segregation," IEEE Electron Device Letters, vol. 35, no. 1, pp.6-8, 2014.
[8] Q. Zhang et al., "Drive-Current Enhancement in Ge n-Channel MOSFET Using Laser Annealing for Source/Drain Activation," IEEE Electron Device Letters, vol. 27, no. 9, pp.728-730, 2006.
[9] W.-H. Chang, H. Ota and T. Maeda, "Gate-First High-Performance Germanium nMOSFET and pMOSFET Using Low Thermal Budget Ion Implantation After Germanidation Technique," IEEE Electron Device Letters, vol. 37, no. 3, pp.253-256, 2016.
[10] Z. Li et al., "Low Electron Schottky Barrier Height of NiGe/Ge Achieved by Ion Implantation After Germanidation Technique," IEEE Electron Device Letters, vol. 33, no. 12, pp.1687-1689, 2012.
[11] N. Tsuji, et al., ''New erase scheme for DINOR Flash Memory Enhancing Erase/Write Cycling Endurance Characetristics,'' Technical Digest of IEDM, 1994, p.53.
[12] T. P. Ma and P. V. Dressendorfer, ''Ionizing Radiation Effects in MOS Devices and Circuits,'' John Wiley & Sons, 1989.
[13] M. Gaillardin et al., "Total ionizing dose effects on triple-gate FETs," IEEE transactions on nuclear science, vol. 53, no. 6, pp.3158-3165, 2006.
[14] Z. Liu et al., "Influence of poly region extended into field oxide on total ionizing dose effect for deep submicron MOSFET," in 2011 12th European Conference on Radiation and Its Effects on Components and Systems, 2011: IEEE, pp.28-35.
[15] C. Peng et al., "Total-ionizing-dose induced coupling effect in the 130-nm PDSOI I/O nMOSFETs," IEEE Electron Device Letters, vol. 35, no. 5, pp.503-505, 2014.
[16] C. W. Gwyn, R. Stulen, and D. Attwood, "Extreme ultraviolet lithography," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, vol. 16, no. 6, pp.3142-3149, 1998.
[17] E. Stassinopoulos and J.P. Raymond, "The space radiation environment for electronics," Proceedings of the IEEE, vol. 76, no. 11, pp.1423-1442, 1988.
[18] O. M. Haraz, A. Elboushi, S. A. Alshebeili, "Dense dielectric patch array antenna with improved radiation characteristics using EBG ground structure and dielectric superstrate for future 5G cellular networks," IEEE Access, vol. 2, pp.909-913, 2014.
[19] J. R. Schwank et al., "Radiation effects in MOS oxides," IEEE Transactions on Nuclear Science, vol. 55, no. 4, pp. 1833-1853, 2008.
[20] K. Schroder, "Semiconductor material and device characterization," New York :/Wiley,/c. pp.379-386. 1998.
[21] S.M. Sze et al., "Semiconductor devices: physics and technology, 2nd Ed.," John Wiley, pp.218-220, pp.313-325, 2002.
[22] Glenn F. Knoll et al., "Radiation Detection and measurement 3rd ed.,'' John Wiley & Sons, Inc. ch.11, pp.399, pp.751-752, 1999.
[23] T. P. Ma et al., ''Ionizing radiation effects in MOS devices and circuit,'' New York Wiley, c, pp.3-35, 1989.
[24] T.L Wu, " The Study Of MOSFET Gamma-Ray Dosimeter," 清華大學核子工程系碩士論文, pp.9-29, 1995.
[25] D.K.Schroder, "Negative bias temperature instability: What do we understand?," Microelectronics Reliability, vol. 47, pp. 841–852, 2007.
[26] S. Mahapatra, M.A.Alam, P. B. Kumar, T. R. Dalei, D.Varghese and D.Saha, ''Negative Bias Temperature Instability in CMOS Devices,'' Microelectronic Engineering, vol. 80, pp.114-121, 2005.
[27] J. F. Zhang, J. Ma, W. Zhang and Z. Ji, ''Defects and lifetime prediction for GE pMOSFETs under AC NBTI stresses,'' China Semiconductor Technology International Conference, 2017.
[28] M. Alam, ''A critical examination of the mechanics of dynamic NBTI for p-MOSFETs,'' IEDM, pp.345-348, 2003.
[29] S. Chakravarthi, A. Krishnan, V. Reddy, C.F. Machala and S. Krishnan, ''A comprehensive framework for predictive modeling of negative bias temperature instability,'' in: Proc., IRPS, pp.273-282, 2004.
[30] H-C Lin, D-Y Lee and T-Y Huang, ''Breakdown Modes and Theor Evolution in Ultrathin Gate Oxide,'' Applied Physics Phy. vol.41,2002.
[31] J. S. Bruglar and P. G. A. Jespers, ''Charge Pumping in MOS Devices,'' IEEE Transactions on Electron Devices, vol.16, p.297., 1969.
[32] G. Groeseneken, H. E. Maes, N. Beltran and R. F. De Keersmaecker, ''A Reliable Approach to Charge-Pumping Measurements in MOS Transistors,'' IEEE Transactions on Electron Devices, vol.31, p.42., 1984.
[33] L. M. Terman, "An investigation of surface states at a Si-SiO2 interface employing MOS diodes", Solid-State Electron., vol. 5, pp. 285, 1962.
[34] M.Houssa, M.Aoulaiche, S. D. Gendt, G.Groeseneken and M.M.Heyns, '' Negative bias temperature instabilities in HfSiO(N)-based MOSFETs: Electrical characterization and modeling,'' Microelectronics Reliability, vol47, p880-889, 2007.
[35] P. J. M and P. S. Winokur, ''Simple Technique for Separating the Effects of Interface Traps and Trapped Oxide Charge in Metal-Oxide-SemiconductorTransistor,'' Applied Physics Letters, p.133,1986.
[36] K. Schroder, ''Semiconductor Material and Devices Characterization,'' John Wiley & Sons, 1998.
[37] H. Aono, E. Murakami, T. Mizuno, H. Sato, K. Haraguchi, M. Kato and K. Kubota, ''A Comprehensive Study of FN Degradation for Driver MOSFETs in Nonvolatile Memory Circuit,'' IEEE International Reliability Physics Symposium Proceedings, 2006.
[38] Angada B. Sachid and Chenming Hu, "A little known benefit of FinFET over planar MOSFET in high performance circuits at advanced technology nodes," IEEE International SOI Conference (SOI): IEEE, pp.1-2 , 2012.
[39] Y. Hashim, "A Review on Transistors in Nano Dimensions," International Journal of Engineering Technology and Sciences (IJETS), vol. 4, no. 1, pp. 8-18, 2015.
[40] D. Nagy et al., "FinFET versus gate-all-around nanowire FET: Performance, scaling, and variability," IEEE Journal of the Electron Devices Society, vol. 6, pp. 332-340, 2018.
[41] G. Qu, D. Min, Z. Zhao, M. Fréchette and S. Li, "Radiation Effect on the Electron Transport Properties of SiO2/Si Interface: Role of Si Dangling-Bond Defects and Oxygen Vacancy," IEEE 2nd International Conference on Dielectrics (ICD), pp. 1-4., 2018.
[42] J. Huang et al., ''Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application,'' Symposium on VLSI Technology, 2009.
[43] I. Chatterjee et al., '' Geometry Dependence of Total-Dose Effects in Bulk FinFETs,'' IEEE Transactions on Nuclear Science, 2014.
[44] J. P. Colinge et al., '' Radiation Dose Effects in Trigate SOI MOS Transistors,'' IEEE Transactions on Nuclear Science, vol.53, no.6, 2006.
[45] T. D. Haeffner et al., '' Comparison of Total-Ionizing-Dose Effects in Bulk and SOI FinFETs at 90 and 295 K,'' IEEE Transactions on Nuclear Science, vol.66, Issue.6, 2019.
[46] X.Guo, Y. Feng, Q. Liu, H. Wang, C. Li, Z. Hu and X-He, ''Current Kink and Capacitance Frequency Dispersion in Silicon PIN Photodiodes,'' IEEE Journal of the Electron Devices Society, vol. PP, no. 99, pp.1–1, 2017.
[47] A.Vais et al., ''A New Quality Metric for III-V/High-k MOS Gate Stacks Based on the Frequency Dispersion of Accumulation Capacitance and the CET,'' IEEE Electron Device Letters, vol. 38, no. 3. pp. 318–321, 2017.
[48] A.Kumar, B. Patel and J. B. Laloe, ''Strategies for reducing particle defects in ALD TiN and RFPVD Ti processes,'' International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), pp.51–54, 2017.
[49] S.-H. Yi, Kuei-Shu Chang-Liao, C-W Hsu and J-Y Huang, "Improved Electrical Characteristics of ~0.5 nm EOT Ge pMOSFET With GeON Interfacial Layer Formed by NH3 Plasma and Microwave Annealing Treatments," IEEE Electron Device Letters, vol. 39, no. 9, pp. 1278-1281, 2018.
[50] M.-C. Chen, K.-M. Chang , S-Y Huang and K.-C. Chang, "A low-temperature method for improving the performance of sputter-deposited ZnO thin-film transistors with supercritical fluid," Applied Physics Letters, vol. 94, no. 16, 2009.
[51] L.-F. Teng, P.-T. Lia. and W.-Y. Wang, "Electrical Performance Enhancement of Al–Zn-Sn–O Thin Film Transistor by Supercritical Fluid Treatment," IEEE Electron Device Letters, vol. 34, no. 9, pp. 1154-1156, 2013
[52] C. H. Chen et al., "Tungsten nanocrystal memory devices improved by supercritical fluid treatment," Applied Physics Letters, vol. 91, no. 23, 2007.
[53] P. T. Liu et al., "Effects of postgate dielectric treatment on germanium-based metal-oxide-semiconductor device by supercritical fluid technology," Appl Phys Lett, vol. 96, no. 11, p. 112902, 2010.
[54] P.-T. Liu, C.-T. Tsai, and P.-Y. Yang, "Effects of supercritical CO2 fluid on sputter-deposited hafnium oxide," Applied Physics Letters, vol. 90, no. 22, 2007.
[55] T.-M. Tsai et al., "Origin of Hopping Conduction in Sn-Doped Silicon Oxide RRAM With Supercritical CO2 Fluid Treatment," IEEE Electron Device Letters, vol. 33, no. 12, pp. 1693-1695, 2012.
[56] D. B. Ruan et al., "Performance Enhancement for Tungsten-Doped Indium Oxide Thin Film Transistor by Hydrogen Peroxide as Cosolvent in Room-Temperature Supercritical Fluid Systems," ACS Appl Mater Interfaces, vol. 11, no. 25, pp.22521-22530, 2019.
[57] H. Aono et al., ''Modeling of NBTI Degradation and Its Impact on Electric Field Dependence of the Lifetime'', IEEE International Reliability Physics Symposium. Proceedings, 2004.
[58] S. S. Chung et al., ''A novel and direct determination of the interface traps in sub-100 nm CMOS devices with direct tunneling regime (12-16 Å) gate oxide,'' Symp. VLSI Tech. Dig., pp. 74-75, 2002.
[59] P. Masson, J.-L. Autran and J. Brini, ''On the tunneling component of charge pumping current in ultrathin gate oxide MOSFETs,'' IEEE Electron Device Lett., vol. 20, no. 2, pp. 92-94, 1999.
[60] P. Milić, M. M. Pejović and A. B. Jakšić, ''Radiation-sensitive field effect transistor response to gamma-ray irradiation'', Nuclear Technology and Radiation Protection, vol26, Issue 26, pp.25-31, 2011.
[61] P. Heremans, J. Witters, G. Groeseneken and H. E. Maes, ''Analysis of the Charge Pumping Technique and Its Application for the Evaluation of MOSFET Degradation'' IEEE Trans. Electron Dev. 36, pp.1318–1335, 1989.
[62] J.L. Autran and C. Chabrerie, '' Use of the Charge Pumping Technique with a Sinusoidal Gate Waveform,'' Solid-State Electron., pp.1394–1395, 1996.
[63] C.-H. Chang, ''Determination of Channel-Hot-Carrier Induced Interface Traps and Oxide Charge in MOSFET’s With High-K Gate Dielectric, ''清華大學工程與系統科學碩士論文, p24, 2005.
[64] T.-S. Liu, "Study and Application of Semiconductor Radiation Dectors for Nuclear Power Plant," 清華大學工程與系統科學碩士論文, pp.26, 2005.
[66] S.-T. Hsiang, "Detection of Interface and Border Trap Distributions and Reliability Analysis for Ge MOSFETs by Charge Pumping Technique, " 清華大學工程與系統科學碩士論文, 2015.
[67] S.M. Sze and Kwok K. Ng, "Physics of Semiconductor Devices," John Wiley & Sons , pp215-220, 2006.